| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 32 return EnableSchedModel && SchedModel.hasInstrSchedModel(); in hasInstrSchedModel()
57 SchedModel = sm; in init()
62 unsigned NumRes = SchedModel.getNumProcResourceKinds(); in init()
64 ResourceLCM = SchedModel.IssueWidth; in init()
66 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
70 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
72 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits; in init()
111 if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) { in getDefLatency()
114 return SchedModel.MinLatency; in getDefLatency()
117 return TII->defaultDefLatency(&SchedModel, DefMI); in getDefLatency()
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| D | MachineScheduler.cpp | 988 const TargetSchedModel *SchedModel);
1012 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1014 unsigned getMaxRemainingCount(const TargetSchedModel *SchedModel) const { in getMaxRemainingCount()
1015 if (!SchedModel->hasInstrSchedModel()) in getMaxRemainingCount()
1019 RemainingMicroOps * SchedModel->getMicroOpFactor(), in getMaxRemainingCount()
1029 const TargetSchedModel *SchedModel; member
1095 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"), in SchedBoundary()
1141 const TargetSchedModel *SchedModel; member in __anon029210900411::ConvergingScheduler
1158 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} in ConvergingScheduler()
1201 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init() argument
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| D | MachineTraceMetrics.cpp | 58 SchedModel.init(*ST.getSchedModel(), &ST, TII); in runOnMachineFunction()
749 DepCycle += MTM.SchedModel in computeInstrDepths()
774 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards() argument
798 DepHeight += SchedModel in updatePhysDepsUpwards()
833 const TargetSchedModel &SchedModel, in pushDepHeight() argument
837 UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, in pushDepHeight()
952 Heights, MTM.SchedModel, MTM.TII)) in computeInstrHeights()
981 MTM.SchedModel, MTM.TII, MTM.TRI); in computeInstrHeights()
985 if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII)) in computeInstrHeights()
1055 DepCycle += TE.MTM.SchedModel in getPHIDepth()
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| D | TargetInstrInfo.cpp | 622 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, in defaultDefLatency() argument
627 return SchedModel->LoadLatency; in defaultDefLatency()
629 return SchedModel->HighLatency; in defaultDefLatency()
683 if (ItinData->SchedModel->MinLatency >= 0) in computeDefOperandLatency()
692 return defaultDefLatency(ItinData->SchedModel, DefMI); in computeDefOperandLatency()
737 defaultDefLatency(ItinData->SchedModel, DefMI)); in computeOperandLatency()
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| D | ScheduleDAGInstrs.cpp | 58 SchedModel.init(*ST.getSchedModel(), &ST, TII); in ScheduleDAGInstrs()
268 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
272 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
311 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); in addPhysRegDeps()
389 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); in addVRegDefDeps()
427 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false)); in addVRegUseDeps()
429 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true)); in addVRegUseDeps()
684 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); in initSUnits()
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| D | EarlyIfConversion.cpp | 582 const MCSchedModel *SchedModel; member in __anon41c95d6e0211::EarlyIfConverter
690 unsigned CritLimit = SchedModel->MispredictPenalty/2; in shouldConvertIf()
780 SchedModel = in runOnMachineFunction()
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| D | ScoreboardHazardRecognizer.cpp | 80 IssueWidth = ItinData->SchedModel->IssueWidth; in ScoreboardHazardRecognizer()
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| /external/llvm/include/llvm/CodeGen/ |
| D | TargetSchedule.h | 35 MCSchedModel SchedModel; variable
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; } in getMCSchedModel()
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); } in getProcessorID()
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
88 unsigned getILPWindow() const { return SchedModel.ILPWindow; } in getILPWindow()
96 return SchedModel.getNumProcResourceKinds(); in getNumProcResourceKinds()
101 return SchedModel.getProcResource(PIdx); in getProcResource()
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| D | ScheduleDAGInstrs.h | 79 TargetSchedModel SchedModel; variable
150 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel()
155 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
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| D | MachineTraceMetrics.h | 73 TargetSchedModel SchedModel; variable
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.h | 48 const TargetSchedModel *SchedModel; variable
59 SchedModel(SM), TotalPackets(0) { in VLIWResourceModel()
66 Packet.resize(SchedModel->getIssueWidth()); in VLIWResourceModel()
135 const TargetSchedModel *SchedModel; member
156 DAG(0), SchedModel(0), Available(ID, Name+".A"), in SchedBoundary()
169 SchedModel = smodel; in init()
192 const TargetSchedModel *SchedModel; variable
208 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} in ConvergingVLIWScheduler()
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| D | HexagonMachineScheduler.cpp | 130 if (Packet.size() >= SchedModel->getIssueWidth()) { in reserveResources()
197 SchedModel = DAG->getSchedModel(); in initialize()
200 Top.init(DAG, SchedModel); in initialize()
201 Bot.init(DAG, SchedModel); in initialize()
272 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
273 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
295 unsigned Width = SchedModel->getIssueWidth(); in bumpCycle()
338 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 113 const MCSchedModel *SchedModel; ///< Basic machine properties.
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel), in InstrItineraryData()
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F), in InstrItineraryData()
128 Itineraries(SchedModel->InstrItineraries) {} in InstrItineraryData()
170 return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency; in getStageLatency()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 115 // SchedModel ties these units to a processor for any stand-alone defs
117 // attached to a processor, so SchedModel is not needed.
123 SchedMachineModel SchedModel = ?;
138 SchedMachineModel SchedModel = ?;
175 // SchedModel silences warnings but is ignored.
179 SchedMachineModel SchedModel = ?;
184 // SchedModel ties these resources to a processor.
195 SchedMachineModel SchedModel = ?;
238 // type at the same time. This class is unaware of its SchedModel so
245 // SchedModel ties these resources to a processor.
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| D | TargetSubtargetInfo.h | 54 const TargetSchedModel* SchedModel) const { in resolveSchedClass() argument
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| D | TargetInstrInfo.h | 835 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
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| D | Target.td | 981 // SchedModel - The machine model for scheduling and instruction cost.
983 SchedMachineModel SchedModel = NoSchedModel;
1001 let SchedModel = m;
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| /external/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 110 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU() local
111 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); in getInstrItineraryForCPU()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 136 SchedModel = getSchedModelForCPU(CPUString); in resetSubtargetFeatures()
221 return SchedModel->MispredictPenalty; in getMispredictionPenalty()
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| D | ARMSubtarget.h | 173 const MCSchedModel *SchedModel; variable
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| D | ARMScheduleA9.td | 2009 static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
2282 let SchedModel = CortexA9Model in {
2489 } // SchedModel = CortexA9Model
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 321 if (Packet.size() >= InstrItins->SchedModel->IssueWidth) { in reserveResources()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 45 // SchedModel info for instruction that loads one value and gets the second
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