| /external/llvm/lib/Transforms/Scalar/ |
| D | Sink.cpp | 57 bool SinkInstruction(Instruction *I, SmallPtrSet<Instruction *, 8> &Stores);
134 SmallPtrSet<Instruction *, 8> Stores; in ProcessBlock() local
147 if (SinkInstruction(Inst, Stores)) in ProcessBlock()
157 SmallPtrSet<Instruction *, 8> &Stores) { in isSafeToMove() argument
160 Stores.insert(Inst); in isSafeToMove()
166 for (SmallPtrSet<Instruction *, 8>::iterator I = Stores.begin(), in isSafeToMove()
167 E = Stores.end(); I != E; ++I) in isSafeToMove()
220 SmallPtrSet<Instruction *, 8> &Stores) { in SinkInstruction() argument
222 if (!isSafeToMove(Inst, AA, Stores)) in SinkInstruction()
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| /external/oprofile/events/mips/r10000/ |
| D | events | 11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
34 … minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with…
36 event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores o…
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | ldp-offset-predictable.txt | 3 # Stores are OK.
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| D | ldp-preind.predictable.txt | 7 # Stores from duplicated registers should be fine.
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| D | ldp-postind.predictable.txt | 7 # Stores from duplicated registers should be fine.
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| /external/oprofile/events/mips/5K/ |
| D | events | 10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional store…
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 551 SmallVector<SDValue, 8> Stores; in ExpandStore() local
564 Stores.push_back(Store); in ExpandStore()
567 &Stores[0], Stores.size()); in ExpandStore()
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| D | LegalizeDAG.cpp | 343 SmallVector<SDValue, 8> Stores; in ExpandUnalignedStore() local
353 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, in ExpandUnalignedStore()
375 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, in ExpandUnalignedStore()
383 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedStore()
384 Stores.size()); in ExpandUnalignedStore()
462 SmallVector<SDValue, 8> Stores; in ExpandUnalignedLoad() local
475 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, in ExpandUnalignedLoad()
495 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, in ExpandUnalignedLoad()
500 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedLoad()
501 Stores.size()); in ExpandUnalignedLoad()
[all …]
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| /external/oprofile/events/ia64/itanium2/ |
| D | events | 30 #event:0xd1 counters:0,1,2,3 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
32 …vent:0xd0 counters:0,1,2,3 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
104 event:0xd1 counters:1 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
106 event:0xd0 counters:1 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 754 SDValue Stores[4]; in LowerSTORE() local
767 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in LowerSTORE()
771 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT); in LowerSTORE()
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| /external/zlib/src/old/ |
| D | visual-basic.txt | 83 Private lngpvtPcnSml As Long 'Stores value for 'lngPercentSmaller'
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 2456 ValueVector Stores; in canVectorizeMemory() local
2490 Stores.push_back(St); in canVectorizeMemory()
2500 if (!Stores.size()) { in canVectorizeMemory()
2518 for (I = Stores.begin(), IE = Stores.end(); I != IE; ++I) { in canVectorizeMemory()
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| /external/oprofile/events/i386/core_2/ |
| D | unit_masks | 138 0x02 Stores
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| /external/oprofile/events/mips/24K/ |
| D | events | 97 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
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| /external/chromium/chrome/browser/automation/ |
| D | ui_controls_mac.mm | 214 // Stores the current mouse location on the screen. So that we can use it
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| /external/oprofile/events/mips/34K/ |
| D | events | 105 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsPowerPC.td | 130 // Stores. These don't map directly to GCC builtins because they represent the
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| /external/oprofile/events/ppc/e500/ |
| D | events | 37 event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores compl…
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| /external/oprofile/events/ppc/e500v2/ |
| D | events | 37 event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores compl…
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| /external/oprofile/events/mips/1004K/ |
| D | events | 113 event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 254 let PPC970_Unit = 2 in { // Stores.
625 // Stores.
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| D | PPCSchedule440.td | 97 // update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
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| D | PPCInstrInfo.td | 850 // Unindexed (r+i) Stores.
869 // Unindexed (r+i) Stores with Update (preinc).
906 // Indexed (r+r) Stores.
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| /external/oprofile/events/ppc64/970/ |
| D | event_mappings | 356 #Group 36 pm_mark3, Marked Stores Processing Flow
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| /external/oprofile/events/ppc64/970MP/ |
| D | event_mappings | 361 #Group 36 pm_mark3, Marked Stores Processing Flow
|