1# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s 2 3# None of these instructions should be classified as unpredictable: 4 5# CHECK-NOT: potentially undefined instruction encoding 6 7# Stores from duplicated registers should be fine. 80xe3 0x0f 0x80 0xa9 9# CHECK: stp x3, x3, [sp, #0]! 10 11# d5 != x5 so "ldp d5, d6, [x5, #24]!" is fine. 120xa5 0x98 0xc1 0x6d 13# CHECK: ldp d5, d6, [x5, #24]! 14 15# xzr != sp so "stp xzr, xzr, [sp, #8]!" is fine. 160xff 0xff 0x80 0xa9 17# CHECK: stp xzr, xzr, [sp, #8]! 18