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Searched refs:X86 (Results 1 – 25 of 209) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp95 ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
96 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
98 ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
99 : X86::ADJCALLSTACKUP32)), in X86InstrInfo()
103 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
105 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, in X86InstrInfo()
108 { X86::ADC64rr, X86::ADC64mr, 0 }, in X86InstrInfo()
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DX86RegisterInfo.cpp60 ? X86::RIP : X86::EIP), in X86RegisterInfo()
64 ? X86::RIP : X86::EIP)), in X86RegisterInfo()
75 StackPtr = X86::RSP; in X86RegisterInfo()
76 FramePtr = X86::RBP; in X86RegisterInfo()
79 StackPtr = X86::ESP; in X86RegisterInfo()
80 FramePtr = X86::EBP; in X86RegisterInfo()
85 BasePtr = Is64Bit ? X86::RBX : X86::ESI; in X86RegisterInfo()
92 case X86::EBX: case X86::RBX: return 1; in getCompactUnwindRegNum()
93 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
94 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
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DX86FloatingPoint.cpp118 unsigned Reg = *I - X86::FP0; in calcLiveInMask()
223 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
252 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
261 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
318 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
319 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
332 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
333 return Reg - X86::FP0; in getFPReg()
344 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); in runOnMachineFunction()
346 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { in runOnMachineFunction()
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DX86MCInstLower.cpp243 if (Reg == 0 || Reg == X86::RIP) continue; in lower_lea64_32mem()
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
306 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
379 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand. in Lower()
382 case X86::LEA64r: in Lower()
383 case X86::LEA16r: in Lower()
384 case X86::LEA32r: in Lower()
386 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
388 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
391 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; in Lower()
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DX86FrameLowering.cpp61 return X86::SUB64ri8; in getSUBriOpcode()
62 return X86::SUB64ri32; in getSUBriOpcode()
65 return X86::SUB32ri8; in getSUBriOpcode()
66 return X86::SUB32ri; in getSUBriOpcode()
73 return X86::ADD64ri8; in getADDriOpcode()
74 return X86::ADD64ri32; in getADDriOpcode()
77 return X86::ADD32ri8; in getADDriOpcode()
78 return X86::ADD32ri; in getADDriOpcode()
83 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode()
99 X86::EAX, X86::EDX, X86::ECX, 0 in findDeadCallerSavedReg()
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DX86ISelDAGToDAG.cpp91 return RegNode->getReg() == X86::RIP; in isRIPRelative()
558 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; in EmitSpecialCodeForMain()
586 if (!X86::isOffsetSuitableForCodeModel(Val, M, in FoldOffsetIntoAddress()
614 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in MatchLoadInAddress()
617 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in MatchLoadInAddress()
682 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); in MatchWrapper()
747 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); in MatchAddress()
1314 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectAddr()
1316 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectAddr()
1459 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); in SelectTLSADDRAddr()
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DX86FastISel.cpp189 Opc = X86::MOV8rm; in X86FastEmitLoad()
190 RC = &X86::GR8RegClass; in X86FastEmitLoad()
193 Opc = X86::MOV16rm; in X86FastEmitLoad()
194 RC = &X86::GR16RegClass; in X86FastEmitLoad()
197 Opc = X86::MOV32rm; in X86FastEmitLoad()
198 RC = &X86::GR32RegClass; in X86FastEmitLoad()
202 Opc = X86::MOV64rm; in X86FastEmitLoad()
203 RC = &X86::GR64RegClass; in X86FastEmitLoad()
207 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
208 RC = &X86::FR32RegClass; in X86FastEmitLoad()
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DX86Subtarget.cpp188 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } in AutoDetectSubtargetFeatures()
189 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); } in AutoDetectSubtargetFeatures()
190 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } in AutoDetectSubtargetFeatures()
191 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } in AutoDetectSubtargetFeatures()
192 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); } in AutoDetectSubtargetFeatures()
193 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);} in AutoDetectSubtargetFeatures()
194 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);} in AutoDetectSubtargetFeatures()
195 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);} in AutoDetectSubtargetFeatures()
196 if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); } in AutoDetectSubtargetFeatures()
203 ToggleFeature(X86::FeaturePCLMUL); in AutoDetectSubtargetFeatures()
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DX86CodeEmitter.cpp154 if (Desc.getOpcode() == X86::MOVPC32r) in runOnMachineFunction()
155 emitInstruction(*I, &II->get(X86::POP32r)); in runOnMachineFunction()
229 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); in determineREX()
270 X86::reloc_pcrel_word, MBB)); in emitPCRelativeBlockAddress()
284 if (Reloc == X86::reloc_picrel_word) in emitGlobalAddress()
286 else if (Reloc == X86::reloc_pcrel_word) in emitGlobalAddress()
296 if (Reloc == X86::reloc_absolute_dword) in emitGlobalAddress()
308 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; in emitExternalSymbolAddress()
318 if (Reloc == X86::reloc_absolute_dword) in emitExternalSymbolAddress()
332 if (Reloc == X86::reloc_picrel_word) in emitConstPoolAddress()
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DX86ISelLowering.cpp231 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
232 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
233 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
235 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
560 setExceptionPointerRegister(X86::RAX); in X86TargetLowering()
561 setExceptionSelectorRegister(X86::RDX); in X86TargetLowering()
563 setExceptionPointerRegister(X86::EAX); in X86TargetLowering()
564 setExceptionSelectorRegister(X86::EDX); in X86TargetLowering()
602 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
603 addRegisterClass(MVT::f64, &X86::FR64RegClass); in X86TargetLowering()
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DX86SelectionDAGInfo.cpp96 ValReg = X86::AX; in EmitTargetCodeForMemset()
101 ValReg = X86::EAX; in EmitTargetCodeForMemset()
106 ValReg = X86::RAX; in EmitTargetCodeForMemset()
112 ValReg = X86::AL; in EmitTargetCodeForMemset()
129 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); in EmitTargetCodeForMemset()
133 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX : in EmitTargetCodeForMemset()
134 X86::ECX, in EmitTargetCodeForMemset()
137 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI : in EmitTargetCodeForMemset()
138 X86::EDI, in EmitTargetCodeForMemset()
152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
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DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
10 // This file describes the X86 Register file, defining the registers themselves,
17 let Namespace = "X86";
23 let Namespace = "X86" in {
41 // variations by target as well. Currently the first entry is for X86-64,
42 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
43 // and debug information on X86-32/Darwin)
59 // X86-64 only, requires REX.
90 // X86-64 only, requires REX.
114 // X86-64 only, requires REX
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86AsmBackend.cpp47 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
48 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
49 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
50 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
75 return X86::NumTargetFixupKinds; in getNumFixupKinds()
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { in getFixupKindInfo()
130 case X86::JAE_1: return X86::JAE_4; in getRelaxedOpcodeBranch()
131 case X86::JA_1: return X86::JA_4; in getRelaxedOpcodeBranch()
132 case X86::JBE_1: return X86::JBE_4; in getRelaxedOpcodeBranch()
133 case X86::JB_1: return X86::JB_4; in getRelaxedOpcodeBranch()
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DX86BaseInfo.h26 namespace X86 {
597 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
598 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
599 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: in isX86_64ExtendedReg()
600 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: in isX86_64ExtendedReg()
601 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: in isX86_64ExtendedReg()
602 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: in isX86_64ExtendedReg()
603 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: in isX86_64ExtendedReg()
604 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: in isX86_64ExtendedReg()
605 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: in isX86_64ExtendedReg()
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DX86MCCodeEmitter.cpp47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; in is64BitMode()
52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; in is32BitMode()
167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand()
168 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand()
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
173 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand()
183 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand()
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
188 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) in Is64BitMemOperand()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp36 case X86::INSERTPSrr: in EmitAnyX86InstComments()
37 case X86::VINSERTPSrr: in EmitAnyX86InstComments()
44 case X86::MOVLHPSrr: in EmitAnyX86InstComments()
45 case X86::VMOVLHPSrr: in EmitAnyX86InstComments()
52 case X86::MOVHLPSrr: in EmitAnyX86InstComments()
53 case X86::VMOVHLPSrr: in EmitAnyX86InstComments()
60 case X86::PALIGNR128rr: in EmitAnyX86InstComments()
61 case X86::VPALIGNR128rr: in EmitAnyX86InstComments()
64 case X86::PALIGNR128rm: in EmitAnyX86InstComments()
65 case X86::VPALIGNR128rm: in EmitAnyX86InstComments()
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/external/llvm/test/CodeGen/X86/
Dh-registers-0.ll1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64
3 ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
9 ; X86-64: bar64:
10 ; X86-64: shrq $8, %rdi
11 ; X86-64: incb %dil
19 ; X86-32: bar64:
20 ; X86-32: incb %ah
29 ; X86-64: bar32:
30 ; X86-64: shrl $8, %edi
31 ; X86-64: incb %dil
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Dmemset.ll1 …lc < %s -march=x86 -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
14 ; X86: movl $0,
15 ; X86: movl $0,
16 ; X86: movl $0,
17 ; X86: movl $0,
18 ; X86: movl $0,
19 ; X86: movl $0,
20 ; X86: movl $0,
21 ; X86: movl $0,
22 ; X86-NOT: movl $0,
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Dmemcpy-2.ll5 …c < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64
42 ; X86-64: t1:
43 ; X86-64: movaps _.str(%rip), %xmm0
44 ; X86-64: movaps %xmm0
45 ; X86-64: movb $0
46 ; X86-64: movq $0
82 ; X86-64: t2:
83 ; X86-64: movaps (%rsi), %xmm0
84 ; X86-64: movaps %xmm0, (%rdi)
129 ; X86-64: t3:
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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp56 namespace X86 { namespace
159 #define ENTRY(x) X86::x, in translateRegister()
351 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri && in translateImmediate()
352 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri && in translateImmediate()
353 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri && in translateImmediate()
354 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri && in translateImmediate()
355 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri && in translateImmediate()
356 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri && in translateImmediate()
357 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri && in translateImmediate()
358 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri && in translateImmediate()
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/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp89 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; in is64BitMode()
92 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); in SwitchMode()
383 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX32()
387 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY32()
391 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX64()
395 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY64()
544 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; in isSrcOp()
547 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && in isSrcOp()
554 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; in isDstOp()
557 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) && in isDstOp()
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/external/clang/test/CodeGenObjC/
Dvariadic-sends.m1 …own -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-X86-32 %s
2 …own -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-X86-64 %s
11 // CHECK-X86-32: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)
12 // CHECK-X86-64: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)
17 // CHECK-X86-32: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)
18 // CHECK-X86-64: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)
23 …// CHECK-X86-32: call void (i8*, i8*, i32, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to vo…
24 …// CHECK-X86-64: call void (i8*, i8*, i32, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to vo…
31 …// CHECK-X86-32: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper to vo…
32 …// CHECK-X86-64: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper to vo…
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Dobjc2-weak-import-attribute.m1 …lang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-X86-64 %s
31 // CHECK-X86-64: OBJC_METACLASS_$_WeakRootClass" = extern_weak global
32 // CHECK-X86-64: OBJC_METACLASS_$_WeakClass" = extern_weak global
33 // CHECK-X86-64: OBJC_CLASS_$_WeakClass" = extern_weak global
34 // CHECK-X86-64: OBJC_CLASS_$_WeakClass1" = extern_weak global
35 // CHECK-X86-64: OBJC_CLASS_$_WeakClass3" = extern_weak global
48 // CHECK-NOT-X86-64: OBJC_METACLASS_$_Root" = extern_weak global
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c83 GENOFFSET(X86,x86,EAX); in foo()
84 GENOFFSET(X86,x86,EBX); in foo()
85 GENOFFSET(X86,x86,ECX); in foo()
86 GENOFFSET(X86,x86,EDX); in foo()
87 GENOFFSET(X86,x86,ESI); in foo()
88 GENOFFSET(X86,x86,EDI); in foo()
89 GENOFFSET(X86,x86,EBP); in foo()
90 GENOFFSET(X86,x86,ESP); in foo()
91 GENOFFSET(X86,x86,EIP); in foo()
92 GENOFFSET(X86,x86,CS); in foo()
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/external/llvm/
DAndroid.mk57 lib/Target/X86 \
58 lib/Target/X86/AsmParser \
59 lib/Target/X86/InstPrinter \
60 lib/Target/X86/Disassembler \
61 lib/Target/X86/MCTargetDesc \
62 lib/Target/X86/TargetInfo \
63 lib/Target/X86/Utils

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