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/external/llvm/lib/Target/ARM/
DARMSchedule.td13 def IIC_iALUx : InstrItinClass;
14 def IIC_iALUi : InstrItinClass;
15 def IIC_iALUr : InstrItinClass;
16 def IIC_iALUsi : InstrItinClass;
17 def IIC_iALUsir : InstrItinClass;
18 def IIC_iALUsr : InstrItinClass;
19 def IIC_iBITi : InstrItinClass;
20 def IIC_iBITr : InstrItinClass;
21 def IIC_iBITsi : InstrItinClass;
22 def IIC_iBITsr : InstrItinClass;
[all …]
/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
46 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
52 def WriteLoad : SchedWrite;
53 def WriteStore : SchedWrite;
54 def WriteMove : SchedWrite;
84 def IIC_DEFAULT : InstrItinClass;
85 def IIC_ALU_MEM : InstrItinClass;
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DX86RegisterInfo.td24 def sub_8bit : SubRegIndex;
25 def sub_8bit_hi : SubRegIndex;
26 def sub_16bit : SubRegIndex;
27 def sub_32bit : SubRegIndex;
28 def sub_xmm : SubRegIndex;
47 def AL : X86Reg<"al", 0>;
48 def DL : X86Reg<"dl", 2>;
49 def CL : X86Reg<"cl", 1>;
50 def BL : X86Reg<"bl", 3>;
54 def AH : X86Reg<"ah", 4>;
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def Named : Decl<1>;
15 def Namespace : DDecl<Named>, DeclContext;
16 def UsingDirective : DDecl<Named>;
17 def NamespaceAlias : DDecl<Named>;
18 def Label : DDecl<Named>;
19 def Type : DDecl<Named, 1>;
20 def TypedefName : DDecl<Type, 1>;
21 def Typedef : DDecl<TypedefName>;
22 def TypeAlias : DDecl<TypedefName>;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def : DiagGroup<"address">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
25 def ArrayBounds : DiagGroup<"array-bounds">;
26 def ArrayBoundsPointerArithmetic : DiagGroup<"array-bounds-pointer-arithmetic">;
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Darm_neon.td17 def OP_NONE : Op;
18 def OP_UNAVAILABLE : Op;
19 def OP_ADD : Op;
20 def OP_ADDL : Op;
21 def OP_ADDW : Op;
22 def OP_SUB : Op;
23 def OP_SUBL : Op;
24 def OP_SUBW : Op;
25 def OP_MUL : Op;
26 def OP_MLA : Op;
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DDiagnosticLexKinds.td16 def null_in_string : Warning<"null character(s) preserved in string literal">,
18 def null_in_char : Warning<"null character(s) preserved in character literal">,
20 def null_in_file : Warning<"null character ignored">, InGroup<NullCharacter>;
21 def warn_nested_block_comment : Warning<"'/*' within block comment">,
23 def escaped_newline_block_comment_end : Warning<
26 def backslash_newline_space : Warning<
31 def warn_cxx98_compat_less_colon_colon : Warning<
36 def trigraph_ignored : Warning<"trigraph ignored">, InGroup<Trigraphs>;
37 def trigraph_ignored_block_comment : Warning<
39 def trigraph_ends_block_comment : Warning<"trigraph ends block comment">,
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DDiagnosticParseKinds.td16 def w_asm_qualifier_ignored : Warning<"ignored %0 qualifier on asm">,
18 def warn_file_asm_volatile : Warning<
23 def ext_empty_translation_unit : Extension<
26 def warn_cxx98_compat_top_level_semi : Warning<
29 def ext_extra_semi : Extension<
36 def ext_extra_semi_cxx11 : Extension<
39 def warn_extra_semi_after_mem_fn_def : Warning<
43 def ext_duplicate_declspec : ExtWarn<"duplicate '%0' declaration specifier">,
45 def warn_duplicate_declspec : Warning<"duplicate '%0' declaration specifier">,
47 def ext_plain_complex : ExtWarn<
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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DCommentHTMLTags.td7 def Em : Tag<"em">;
8 def Strong : Tag<"strong">;
9 def Tt : Tag<"tt">;
10 def I : Tag<"i">;
11 def B : Tag<"b">;
12 def Big : Tag<"big">;
13 def Small : Tag<"small">;
14 def Strike : Tag<"strike">;
15 def S : Tag<"s">;
16 def U : Tag<"u">;
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DCommentCommands.td50 def Begin : Command<name> {
55 def End : Command<endCommandName> {
85 def B : InlineCommand<"b">;
86 def C : InlineCommand<"c">;
87 def P : InlineCommand<"p">;
88 def A : InlineCommand<"a">;
89 def E : InlineCommand<"e">;
90 def Em : InlineCommand<"em">;
96 def Brief : BlockCommand<"brief"> { let IsBriefCommand = 1; }
97 def Short : BlockCommand<"short"> { let IsBriefCommand = 1; }
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/external/llvm/test/TableGen/
DNestedForeach.td14 def S#R#M#P : Droid<S, R, M, P>;
20 // CHECK: def C2D0
21 // CHECK: def C2D2
22 // CHECK: def C2D4
23 // CHECK: def C2P0
24 // CHECK: def C2P2
25 // CHECK: def C2P4
26 // CHECK: def C2Q0
27 // CHECK: def C2Q2
28 // CHECK: def C2Q4
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/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
17 def sub_lo : SubRegIndex;
18 def sub_hi : SubRegIndex;
70 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
71 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
72 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
73 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
74 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
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/external/clang/include/clang/Driver/
DOptions.td21 def CompileOnly_Group : OptionGroup<"<CompileOnly group>">;
22 def Action_Group : OptionGroup<"<action group>">;
24 def I_Group : OptionGroup<"<I group>">, Group<CompileOnly_Group>;
25 def L_Group : OptionGroup<"<L group>">, Group<CompileOnly_Group>;
26 def M_Group : OptionGroup<"<M group>">, Group<CompileOnly_Group>;
27 def T_Group : OptionGroup<"<T group>">;
28 def O_Group : OptionGroup<"<O group>">, Group<CompileOnly_Group>;
29 def W_Group : OptionGroup<"<W group>">, Group<CompileOnly_Group>;
30 def X_Group : OptionGroup<"<X group>">;
31 def a_Group : OptionGroup<"<a group>">;
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/external/llvm/include/llvm/IR/
DIntrinsicsHexagon.td614 def int_hexagon_SI_to_SXTHI_asrh :
619 def int_hexagon_circ_ldd :
626 def int_hexagon_C2_cmpeq :
631 def int_hexagon_C2_cmpgt :
636 def int_hexagon_C2_cmpgtu :
641 def int_hexagon_C2_cmpeqp :
646 def int_hexagon_C2_cmpgtp :
651 def int_hexagon_C2_cmpgtup :
656 def int_hexagon_A4_rcmpeqi :
661 def int_hexagon_A4_rcmpneqi :
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DIntrinsicsNVVM.td14 def llvm_anyi64ptr_ty : LLVMAnyPointerType<llvm_i64_ty>; // (space)i64*
20 def int_nvvm_clz_i : GCCBuiltin<"__nvvm_clz_i">,
22 def int_nvvm_clz_ll : GCCBuiltin<"__nvvm_clz_ll">,
25 def int_nvvm_popc_i : GCCBuiltin<"__nvvm_popc_i">,
27 def int_nvvm_popc_ll : GCCBuiltin<"__nvvm_popc_ll">,
30 def int_nvvm_prmt : GCCBuiltin<"__nvvm_prmt">,
38 def int_nvvm_min_i : GCCBuiltin<"__nvvm_min_i">,
41 def int_nvvm_min_ui : GCCBuiltin<"__nvvm_min_ui">,
45 def int_nvvm_min_ll : GCCBuiltin<"__nvvm_min_ll">,
48 def int_nvvm_min_ull : GCCBuiltin<"__nvvm_min_ull">,
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DIntrinsicsMips.td16 def mips_v2q15_ty: LLVMType<v2i16>;
17 def mips_v4q7_ty: LLVMType<v4i8>;
18 def mips_q31_ty: LLVMType<i32>;
28 def int_mips_addu_qb : GCCBuiltin<"__builtin_mips_addu_qb">,
30 def int_mips_addu_s_qb : GCCBuiltin<"__builtin_mips_addu_s_qb">,
32 def int_mips_subu_qb : GCCBuiltin<"__builtin_mips_subu_qb">,
34 def int_mips_subu_s_qb : GCCBuiltin<"__builtin_mips_subu_s_qb">,
37 def int_mips_addq_ph : GCCBuiltin<"__builtin_mips_addq_ph">,
39 def int_mips_addq_s_ph : GCCBuiltin<"__builtin_mips_addq_s_ph">,
41 def int_mips_subq_ph : GCCBuiltin<"__builtin_mips_subq_ph">,
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DIntrinsicsPowerPC.td21 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
22 def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>;
23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
25 def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
27 def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
28 def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
29 def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
32 def int_ppc_sync : Intrinsic<[], [], []>;
89 def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">,
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DIntrinsicsX86.td17 def int_x86_int : Intrinsic<[], [llvm_i8_ty]>;
24 def int_x86_3dnow_pavgusb : GCCBuiltin<"__builtin_ia32_pavgusb">,
27 def int_x86_3dnow_pf2id : GCCBuiltin<"__builtin_ia32_pf2id">,
29 def int_x86_3dnow_pfacc : GCCBuiltin<"__builtin_ia32_pfacc">,
32 def int_x86_3dnow_pfadd : GCCBuiltin<"__builtin_ia32_pfadd">,
35 def int_x86_3dnow_pfcmpeq : GCCBuiltin<"__builtin_ia32_pfcmpeq">,
38 def int_x86_3dnow_pfcmpge : GCCBuiltin<"__builtin_ia32_pfcmpge">,
41 def int_x86_3dnow_pfcmpgt : GCCBuiltin<"__builtin_ia32_pfcmpgt">,
44 def int_x86_3dnow_pfmax : GCCBuiltin<"__builtin_ia32_pfmax">,
47 def int_x86_3dnow_pfmin : GCCBuiltin<"__builtin_ia32_pfmin">,
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DIntrinsicsXCore.td16 def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
17 def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],
20 def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
23 def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
25 def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
27 def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
28 def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
29 def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;
30 def int_xcore_geted : Intrinsic<[llvm_i32_ty],[]>;
31 def int_xcore_getet : Intrinsic<[llvm_i32_ty],[]>;
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td24 def sub_even : SubRegIndex;
25 def sub_odd : SubRegIndex;
46 def ICC : SparcCtrlReg<"ICC">;
47 def FCC : SparcCtrlReg<"FCC">;
50 def Y : SparcCtrlReg<"Y">;
53 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
54 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
55 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
56 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
57 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
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/external/llvm/lib/Target/R600/
DAMDILIntrinsics.td69 def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
71 def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
73 def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">,
75 def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">,
77 def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">,
79 def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">,
81 def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">,
83 def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">,
85 def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">,
87 def int_AMDIL_media_bytealign : GCCBuiltin<"__amdil_bytealign">,
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/external/llvm/lib/Target/MBlaze/
DMBlazeIntrinsics.td31 def int_mblaze_fsl_get : GCCBuiltin<"__builtin_mblaze_fsl_get">,
33 def int_mblaze_fsl_aget : GCCBuiltin<"__builtin_mblaze_fsl_aget">,
35 def int_mblaze_fsl_cget : GCCBuiltin<"__builtin_mblaze_fsl_cget">,
37 def int_mblaze_fsl_caget : GCCBuiltin<"__builtin_mblaze_fsl_caget">,
39 def int_mblaze_fsl_eget : GCCBuiltin<"__builtin_mblaze_fsl_eget">,
41 def int_mblaze_fsl_eaget : GCCBuiltin<"__builtin_mblaze_fsl_eaget">,
43 def int_mblaze_fsl_ecget : GCCBuiltin<"__builtin_mblaze_fsl_ecget">,
45 def int_mblaze_fsl_ecaget : GCCBuiltin<"__builtin_mblaze_fsl_ecaget">,
47 def int_mblaze_fsl_nget : GCCBuiltin<"__builtin_mblaze_fsl_nget">,
49 def int_mblaze_fsl_naget : GCCBuiltin<"__builtin_mblaze_fsl_naget">,
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/external/llvm/include/llvm/CodeGen/
DValueTypes.td22 def OtherVT: ValueType<0 , 0>; // "Other" value
23 def i1 : ValueType<1 , 1>; // One bit boolean value
24 def i8 : ValueType<8 , 2>; // 8-bit integer value
25 def i16 : ValueType<16 , 3>; // 16-bit integer value
26 def i32 : ValueType<32 , 4>; // 32-bit integer value
27 def i64 : ValueType<64 , 5>; // 64-bit integer value
28 def i128 : ValueType<128, 6>; // 128-bit integer value
29 def f16 : ValueType<16 , 7>; // 32-bit floating point value
30 def f32 : ValueType<32 , 8>; // 32-bit floating point value
31 def f64 : ValueType<64 , 9>; // 64-bit floating point value
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