Searched refs:getImplicitDefs (Results 1 – 8 of 8) sorted by relevance
492 const uint16_t *getImplicitDefs() const { in getImplicitDefs() function
722 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; in EmitMachineNode()782 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; in EmitMachineNode()817 if (!UsedRegs.empty() || II.getImplicitDefs()) in EmitMachineNode()
438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()516 for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
1195 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()1321 for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) in DelayForLiveRegsBottomUp()2713 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()2750 const uint16_t *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()2757 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
448 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
1101 if (const uint16_t *Defs = (*I)->getImplicitDefs()) in runOnMachineFunction()
522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()