Searched refs:imm5 (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 171 // t_addrmode_is4 := reg + imm5 * 4
183 // t_addrmode_is2 := reg + imm5 * 2
195 // t_addrmode_is1 := reg + imm5
551 // Loads: reg/reg and reg/imm5
563 def i : // reg/imm5
569 // Stores: reg/reg and reg/imm5
580 def i : // reg/imm5
884 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
886 "asr", "\t$Rd, $Rm, $imm5",
887 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
[all …]
|
| D | ARMInstrFormats.td | 1097 let Inst{10-6} = addr{7-3}; // imm5
|
| D | ARMInstrInfo.td | 490 // {4-0} imm5 shift amount.
491 // asr #32 encoded as imm5 == 0.
|
| D | ARMInstrThumb2.td | 35 // {4-0} imm5 shift amount.
|
| /external/valgrind/main/VEX/priv/ |
| D | guest_arm_toIR.c | 1593 UInt imm5 ) /* saturation ceiling */ in armUnsignedSatQ() argument
1595 UInt ceil = (1 << imm5) - 1; // (2^imm5)-1 in armUnsignedSatQ()
1639 UInt imm5, /* saturation ceiling */ in armSignedSatQ() argument
1643 Int ceil = (1 << (imm5-1)) - 1; // (2^(imm5-1))-1 in armSignedSatQ()
1644 Int floor = -(1 << (imm5-1)); // -(2^(imm5-1)) in armSignedSatQ()
2396 UInt sh2, UInt imm5, in mk_EA_reg_plusminus_shifted_reg() argument
2403 vassert(imm5 < 32); in mk_EA_reg_plusminus_shifted_reg()
2409 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5)); in mk_EA_reg_plusminus_shifted_reg()
2410 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); in mk_EA_reg_plusminus_shifted_reg()
2413 if (imm5 == 0) { in mk_EA_reg_plusminus_shifted_reg()
[all …]
|
| D | host_arm_defs.h | 268 UInt imm5; member
277 extern ARMRI5* ARMRI5_I5 ( UInt imm5 );
|
| D | host_mips_defs.h | 282 UInt imm5; member
290 extern MIPSRI5 *MIPSRI5_I5(UInt imm5);
|
| D | host_arm_defs.c | 494 ARMRI5* ARMRI5_I5 ( UInt imm5 ) { in ARMRI5_I5() argument
497 ri5->ARMri5.I5.imm5 = imm5; in ARMRI5_I5()
498 vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed in ARMRI5_I5()
511 vex_printf("%u", ri5->ARMri5.I5.imm5); in ppARMRI5()
2761 UInt imm5 = ri->ARMri5.I5.imm5; in skeletal_RI5() local
2762 vassert(imm5 >= 1 && imm5 <= 31); in skeletal_RI5()
2764 instr |= imm5 << 7; in skeletal_RI5()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 168 bits<5> imm5;
175 let Inst{27-31} = imm5;
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 215 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
224 bits<5> imm5;
231 let Inst{4-0} = imm5;
|
| /external/qemu/ |
| D | arm-dis.c | 2106 long imm5; in print_insn_coprocessor() local
2107 imm5 = ((given & 0x100) >> 4) | (given & 0xf); in print_insn_coprocessor()
2108 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); in print_insn_coprocessor()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 547 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
561 let Inst{9-5} = imm5;
|
| /external/valgrind/main/none/tests/arm/ |
| D | v6intThumb.stdout.exp | 757 LSLS-16 Rd, Rm, imm5
782 LSRS-16 Rd, Rm, imm5
807 ASRS-16 Rd, Rm, imm5
|