Home
last modified time | relevance | path

Searched refs:inb (Results 1 – 25 of 43) sorted by relevance

12

/external/grub/netboot/
Dns8390.c131 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
140 *(dst++) = inb(eth_asic_base + ASIC_PIO);
180 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0) in eth_pio_write()
198 (inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) in eth_pio_write()
204 while((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) in eth_pio_write()
363 inb(0x84); in ns8390_transmit()
367 inb(0x84); in ns8390_transmit()
369 inb(0x84); in ns8390_transmit()
379 inb(0x84); in ns8390_transmit()
383 inb(0x84); in ns8390_transmit()
[all …]
Dni5010.c175 printf("XSTAT %hhX ", inb(EDLC_XSTAT));
176 printf("XMASK %hhX ", inb(EDLC_XMASK));
177 printf("RSTAT %hhX ", inb(EDLC_RSTAT));
178 printf("RMASK %hhX ", inb(EDLC_RMASK));
179 printf("RMODE %hhX ", inb(EDLC_RMODE));
180 printf("XMODE %hhX ", inb(EDLC_XMODE));
181 printf("ISTAT %hhX\n", inb(IE_ISTAT));
225 if (((rcv_stat = inb(EDLC_RSTAT)) & RS_VALID_BITS) != RS_PKT_OK) { in ni5010_poll()
272 while (((xmt_stat = inb(IE_ISTAT)) & IS_EN_XMT) != 0) in ni5010_transmit()
288 inb(IE_RBUF); in rd_port()
[all …]
Dvia-rhine.c749 byMIIAdrbak = inb (byMIIAD); in ReadMII()
750 byMIICRbak = inb (byMIICR); in ReadMII()
757 outb (inb (byMIICR) | 0x40, byMIICR); in ReadMII()
759 byMIItemp = inb (byMIICR); in ReadMII()
764 byMIItemp = inb (byMIICR); in ReadMII()
789 byMIIAdrbak = inb (byMIIAD); in WriteMII()
791 byMIICRbak = inb (byMIICR); in WriteMII()
797 outb (inb (byMIICR) | 0x40, byMIICR); in WriteMII()
799 byMIItemp = inb (byMIICR); in WriteMII()
804 byMIItemp = inb (byMIICR); in WriteMII()
[all …]
Di82586.c504 if (inb(ioaddr) != '*' || inb(ioaddr+1) != '3' in t507_probe1()
505 || inb(ioaddr+2) != 'C' || inb(ioaddr+3) != 'O') in t507_probe1()
507 irq = inb(ioaddr + IRQ_CONFIG) & 0x0f; in t507_probe1()
508 mem_config = inb(ioaddr + MEM_CONFIG); in t507_probe1()
522 if_port = inb(ioaddr + ROM_CONFIG) & 0x80; in t507_probe1()
527 nic->node_addr[i] = inb(ioaddr+i); in t507_probe1()
632 if (inb(ioaddr + 6) != 0x0 || inb(ioaddr + 7) != 0x55) in ni5210_probe1()
643 nic->node_addr[i] = inb(ioaddr+i); in ni5210_probe1()
787 nic->node_addr[i] = inb(ioaddr+i); in exos205_probe1()
Dtiara.c125 while ((inb(ioaddr + DLCR_RECV_MODE) & BUF_EMPTY) == 0) in tiara_reset()
126 inb(ioaddr + BMPR_MEM_PORT); in tiara_reset()
141 if (inb(ioaddr + DLCR_RECV_MODE) & BUF_EMPTY) in tiara_poll()
186 while (currticks() < time && (inb(ioaddr) & (TMT_OK|TMT_16COLL)) == 0) in tiara_transmit()
188 if ((inb(ioaddr) & (TMT_OK|TMT_16COLL)) == 0) in tiara_transmit()
210 nic->node_addr[i] = inb(ioaddr + PROM_ID + i); in tiara_probe1()
Ddepca.c542 nicsr = inb(DEPCA_NICSR); in depca_reset()
673 data = inb(DEPCA_PROM); /* clear counter on DEPCA */ in depca_probe1()
674 data = inb(DEPCA_PROM); /* read data */ in depca_probe1()
676 nicsr = inb(DEPCA_NICSR); in depca_probe1()
681 data = inb(DEPCA_PROM); in depca_probe1()
691 nicsr = ((inb(DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM); in depca_probe1()
702 sum += (u8)(nic->node_addr[i++] = inb(DEPCA_PROM)); in depca_probe1()
703 sum += (u16)((nic->node_addr[i++] = inb(DEPCA_PROM)) << 8); in depca_probe1()
709 chksum = (u8)inb(DEPCA_PROM); in depca_probe1()
710 chksum |= (u16)(inb(DEPCA_PROM) << 8); in depca_probe1()
Deepro.c42 #define SLOW_DOWN inb(0x80);
302 temp_reg = inb(ioaddr + eeprom_reg); in eepro_reset()
310 temp_reg = inb(ioaddr + REG1); in eepro_reset()
314 temp_reg = inb(ioaddr + REG2); /* match broadcast */ in eepro_reset()
316 temp_reg = inb(ioaddr + REG3); in eepro_reset()
351 if ((inb(ioaddr + STATUS_REG) & 0x40) == 0) in eepro_poll()
364 inb(ioaddr + STATUS_REG)); in eepro_poll()
488 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0); in read_eeprom()
511 id = inb(ioaddr + ID_REG); in eepro_probe1()
515 if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40)) in eepro_probe1()
Dsk_g16.c185 #define SK_ROM_ON (inb(SK_POS2) & POS2_CARD)
186 #define SK_ROM_OFF (inb(SK_POS2) | POS2_EPROM)
187 #define SK_RAM_ON (inb(SK_POS2) | POS2_CARD)
188 #define SK_RAM_OFF (inb(SK_POS2) & POS2_EPROM)
755 long offset1, offset0 = inb(ioaddr); in SK_probe()
757 ((offset1 = inb(ioaddr + 1)) == SK_IDHIGH)) in SK_probe()
1110 unsigned char pos0 = inb(SK_POS0), in SK_print_pos()
1111 pos1 = inb(SK_POS1), in SK_print_pos()
1112 pos2 = inb(SK_POS2), in SK_print_pos()
1113 pos3 = inb(SK_POS3), in SK_print_pos()
[all …]
Dtimer.c16 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); in load_timer2()
50 outb((inb(0x61) & ~0x02) | 0x01, 0x61); in calibrate_tsc()
72 } while ((inb(0x61) & 0x20) == 0); in calibrate_tsc()
Drtl8139.c209 *ap++ = inb(ioaddr + MAC0 + i); in rtl8139_probe()
212 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; in rtl8139_probe()
275 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); in read_eeprom()
296 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) in rtl_reset()
395 if (inb(ioaddr + ChipCmd) & RxBufEmpty) { in rtl_poll()
456 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) in rtl_disable()
Dtimer.h54 return ((inb(PPC_PORTB) & PPCB_T2OUT) == 0); in timer2_running()
60 while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) in waiton_timer2()
Dlance.c455 nic->node_addr[i] = inb(ioaddr+LANCE_ETH_ADDR+i); in lance_probe1()
459 dma_channels = ((inb(DMA1_STAT_REG) >> 4) & 0xf) | in lance_probe1()
460 (inb(DMA2_STAT_REG) & 0xf0); in lance_probe1()
529 char offset15, offset14 = inb(ioaddr + 14); in lancepci_probe()
534 ((offset15 = inb(ioaddr + 15)) == 0x57 || offset15 == 0x44)) in lancepci_probe()
540 ((offset15 = inb(ioaddr + 15)) == 0x55 || offset15 == 0x44)) in lancepci_probe()
D3c595.c119 inb(BASE + VX_W1_TX_STATUS); in t595_reset()
193 while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) { in t595_transmit()
271 nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); in t595_poll()
284 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1); in t595_poll()
D3c509.c115 inb(BASE + EP_W1_TX_STATUS); in t509_reset()
185 while ((status=inb(BASE + EP_W1_TX_STATUS)) & TXS_COMPLETE ) { in t509_transmit()
261 nic->packet[rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1); in t509_poll()
273 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1); in t509_poll()
Dtlan.c334 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3))); in TLan_DioRead8()
2184 if (inb(ioaddr + EISA_CR) != 0x1) { /* Check if adapter is enabled */
2193 switch (inb(ioaddr + 0xCC0)) {
3468 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3469 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3470 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
3471 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
3474 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3475 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3476 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
[all …]
Dsmc9000.c216 status = inb(smc9000_base + INTERRUPT); in smc9000_transmit()
234 packet_no = inb(smc9000_base + PNR_ARR + 1); in smc9000_transmit()
282 status = inb(smc9000_base + INTERRUPT); in smc9000_transmit()
/external/kernel-headers/original/asm-mips/
Di8259.h58 irq = inb(PIC_MASTER_CMD) & 7; in i8259_irq()
65 irq = (inb(PIC_SLAVE_CMD) & 7) + 8; in i8259_irq()
77 if(~inb(PIC_MASTER_ISR) & 0x80) in i8259_irq()
/external/grub/stage2/
Dserial.c65 inb (unsigned short port) in inb() function
87 if (inb (serial_hw_port + UART_LSR) & UART_DATA_READY) in serial_hw_fetch()
88 return inb (serial_hw_port + UART_RX); in serial_hw_fetch()
100 while ((inb (serial_hw_port + UART_LSR) & UART_EMPTY_TRANSMITTER) == 0) in serial_hw_put()
Dsmp-imps.c73 inb (unsigned short port) in inb() function
99 return inb (0x71); in cmos_read_byte()
/external/qemu-pc-bios/bochs/bios/
Drombios.c852 static Bit8u inb();
1126 inb(port)
1410 return inb(base_port + UART_LSR) & 0x20;
1422 while (!(inb(base_port + UART_LSR) & 0x40));
1754 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1760 if (inb(0x64) & 0x01) {
1761 inb(0x60);
1777 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1782 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x01);
1786 if ((inb(0x60) != 0x55)){
[all …]
Drombios32.c115 static inline uint8_t inb(int addr) in inb() function
425 r1 = inb(0x61) & 0x10; in delay_ms()
427 r2 = inb(0x61) & 0x10; in delay_ms()
496 if (inb(QEMU_CFG_DATA_PORT) != sig[i]) in qemu_cfg_port_probe()
505 *(buf++) = inb(QEMU_CFG_DATA_PORT); in qemu_cfg_read()
560 return inb(0x71); in cmos_readb()
751 return inb(0xcfc + (addr & 3)); in pci_config_readb()
903 while (inb(0xb3) != 0x00); in smm_init()
2163 inb(QEMU_CFG_DATA_PORT); in smbios_load_field()
2173 inb(QEMU_CFG_DATA_PORT); in smbios_load_field()
[all …]
Drombios32start.S95 inb %dx, %al
/external/qemu-pc-bios/vgabios/
Dvgabios.c64 static Bit8u inb();
915 inb(VGAREG_ACTL_RESET);
955 inb(VGAREG_ACTL_RESET);
972 mmask = inb( VGAREG_SEQU_DATA );
2560 inb(VGAREG_ACTL_RESET);
2568 r=inb( VGAREG_DAC_DATA );
2569 g=inb( VGAREG_DAC_DATA );
2570 b=inb( VGAREG_DAC_DATA );
2585 inb(VGAREG_ACTL_RESET);
2654 crtc_r9 = inb(crtc_addr+1);
[all …]
/external/libxml2/
Dencoding.c349 const unsigned char* inb, int *inlenb) in UTF8ToUTF8() argument
353 if ((out == NULL) || (inb == NULL) || (outlen == NULL) || (inlenb == NULL)) in UTF8ToUTF8()
363 memcpy(out, inb, len); in UTF8ToUTF8()
482 const unsigned char* inb, int *inlenb) in UTF16LEToUTF8() argument
485 const unsigned char* processed = inb; in UTF16LEToUTF8()
487 unsigned short* in = (unsigned short*) inb; in UTF16LEToUTF8()
526 *inlenb = processed - inb; in UTF16LEToUTF8()
547 *inlenb = processed - inb; in UTF16LEToUTF8()
720 const unsigned char* inb, int *inlenb) in UTF16BEToUTF8() argument
723 const unsigned char* processed = inb; in UTF16BEToUTF8()
[all …]
/external/llvm/test/MC/X86/
Dx86-64.s219 inb $161, %al label
248 inb $0x7f label
278 inb (%dx), %al label

12