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Searched refs:is64BitVector (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp285 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1623 bool is64BitVector) { in GetVLDSTAlign() argument
1625 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1701 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1702 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()
1728 if (!is64BitVector) in SelectVLD()
1744 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1745 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1810 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1838 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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DARMISelLowering.cpp3606 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in getCTPOP16BitCounts()
3629 if (VT.is64BitVector()) { in lowerCTPOP16BitElements()
3663 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16; in lowerCTPOP32BitElements()
3671 if (VT.is64BitVector()) { in lowerCTPOP32BitElements()
4238 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
4265 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
4287 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
4312 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
4694 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
5290 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
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/external/llvm/include/llvm/CodeGen/
DValueTypes.h203 bool is64BitVector() const { in is64BitVector() function
649 bool is64BitVector() const { in is64BitVector() function
650 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()