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Searched refs:isKill (Results 1 – 25 of 77) sorted by relevance

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/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp226 if (!UseMO.isKill()) in sink3AddrInstruction()
269 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) { in sink3AddrInstruction()
807 if (MOReg != Reg && (MO.isKill() || in rescheduleMIBelowKill()
858 bool isKill = MO.isKill() || in rescheduleMIBelowKill() local
861 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg))) in rescheduleMIBelowKill()
864 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
992 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
993 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
996 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
1037 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)))) in rescheduleKillAboveMI()
[all …]
DMachineInstrBundle.cpp139 if (MO.isKill()) in finalizeBundle()
148 if (MO.isKill()) in finalizeBundle()
198 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
307 PRI.Kills = MO.isKill(); in analyzePhysReg()
DMachineInstr.cpp130 bool isKill, bool isDead, bool isUndef, in ChangeToRegister() argument
149 IsKill = isKill; in ChangeToRegister()
269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || in print()
290 if (isKill()) { in print()
821 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) in isIdenticalTo()
997 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, in findRegisterUseOperandIdx() argument
1011 if (!isKill || MO.isKill()) in findRegisterUseOperandIdx()
1674 if (MO.isKill()) in addRegisterKilled()
1683 } else if (hasAliases && MO.isKill() && in addRegisterKilled()
1721 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in clearRegisterKills()
DExpandPostRAPseudos.cpp121 MI->getOperand(2).isKill()); in LowerSubregToReg()
165 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp156 bool Reg1IsKill = MI->getOperand(1).isKill(); in commuteInstruction()
157 bool Reg2IsKill = MI->getOperand(2).isKill(); in commuteInstruction()
439 unsigned SrcReg, bool isKill, in StoreRegToStackSlot() argument
449 getKillRegState(isKill)), in StoreRegToStackSlot()
458 getKillRegState(isKill)), in StoreRegToStackSlot()
465 getKillRegState(isKill)), in StoreRegToStackSlot()
474 getKillRegState(isKill)), in StoreRegToStackSlot()
480 getKillRegState(isKill)), in StoreRegToStackSlot()
485 getKillRegState(isKill)), in StoreRegToStackSlot()
490 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
DPPCInstrInfo.h72 unsigned SrcReg, bool isKill, int FrameIdx,
130 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp153 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); in eliminateFrameIndex() local
177 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
198 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
227 .addReg(Reg, getKillRegState(isKill)) in eliminateFrameIndex()
DXCoreInstrInfo.h71 unsigned SrcReg, bool isKill, int FrameIndex,
DXCoreInstrInfo.cpp363 unsigned SrcReg, bool isKill, in storeRegToStackSlot() argument
371 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp82 bool isKill; member
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {} in MemOpQueueEntry()
386 if (memOps[i].Position < insertPos && memOps[i].isKill) { in MergeOpsUpdate()
399 bool isKill = memOps[i].isKill || KilledRegs.count(Reg); in MergeOpsUpdate() local
400 Regs.push_back(std::make_pair(Reg, isKill)); in MergeOpsUpdate()
430 memOps[j].isKill = false; in MergeOpsUpdate()
432 memOps[i].isKill = true; in MergeOpsUpdate()
716 bool BaseKill = MI->getOperand(0).isKill(); in MergeBaseUpdateLSMultiple()
852 bool BaseKill = MI->getOperand(1).isKill(); in MergeBaseUpdateLoadStore()
935 getKillRegState(MO.isKill()))); in MergeBaseUpdateLoadStore()
[all …]
DThumb1InstrInfo.cpp53 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
74 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DThumb1FrameLowering.cpp346 bool isKill = true; in spillCalleeSavedRegisters() local
355 isKill = false; in spillCalleeSavedRegisters()
358 if (isKill) in spillCalleeSavedRegisters()
361 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters()
DThumb1InstrInfo.h48 unsigned SrcReg, bool isKill, int FrameIndex,
DThumb2InstrInfo.h50 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp474 if (MI->getOperand(1).isKill()) in runOnMachineFunction()
479 if (MI->getOperand(2).isKill()) in runOnMachineFunction()
562 localMO.isKill() && feederReg == localMO.getReg()) { in runOnMachineFunction()
624 cmpInstr->getOperand(0).isKill()) in runOnMachineFunction()
627 cmpInstr->getOperand(1).isKill()) in runOnMachineFunction()
DHexagonInstrInfo.h80 unsigned SrcReg, bool isKill, int FrameIndex,
84 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp299 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
308 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
311 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
314 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
DSparcInstrInfo.h92 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h108 unsigned Reg, bool isKill, int Offset) { in addRegOffset() argument
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp36 unsigned SrcReg, bool isKill, int FrameIdx, in storeRegToStackSlot() argument
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
DMSP430InstrInfo.h61 unsigned SrcReg, bool isKill,
/external/llvm/include/llvm/CodeGen/
DMachineOperand.h289 bool isKill() const { in isKill() function
535 bool isKill = false, bool isDead = false,
561 bool isKill = false, bool isDead = false,
570 Op.IsKill = isKill;
DMachineInstr.h642 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
768 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
773 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
775 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.h54 unsigned SrcReg, bool isKill, int FrameIndex,
DMips16InstrInfo.h53 unsigned SrcReg, bool isKill, int FrameIndex,

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