1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "XCoreRegisterInfo.h"
15 #include "XCore.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34
35 #define GET_REGINFO_TARGET_DESC
36 #include "XCoreGenRegisterInfo.inc"
37
38 using namespace llvm;
39
XCoreRegisterInfo(const TargetInstrInfo & tii)40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
42 }
43
44 // helper functions
isImmUs(unsigned val)45 static inline bool isImmUs(unsigned val) {
46 return val <= 11;
47 }
48
isImmU6(unsigned val)49 static inline bool isImmU6(unsigned val) {
50 return val < (1 << 6);
51 }
52
isImmU16(unsigned val)53 static inline bool isImmU16(unsigned val) {
54 return val < (1 << 16);
55 }
56
needsFrameMoves(const MachineFunction & MF)57 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
58 return MF.getMMI().hasDebugInfo() ||
59 MF.getFunction()->needsUnwindTableEntry();
60 }
61
getCalleeSavedRegs(const MachineFunction * MF) const62 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
63 const {
64 static const uint16_t CalleeSavedRegs[] = {
65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
67 0
68 };
69 return CalleeSavedRegs;
70 }
71
getReservedRegs(const MachineFunction & MF) const72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73 BitVector Reserved(getNumRegs());
74 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
75
76 Reserved.set(XCore::CP);
77 Reserved.set(XCore::DP);
78 Reserved.set(XCore::SP);
79 Reserved.set(XCore::LR);
80 if (TFI->hasFP(MF)) {
81 Reserved.set(XCore::R10);
82 }
83 return Reserved;
84 }
85
86 bool
requiresRegisterScavenging(const MachineFunction & MF) const87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
88 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
89
90 // TODO can we estimate stack size?
91 return TFI->hasFP(MF);
92 }
93
94 bool
trackLivenessAfterRegAlloc(const MachineFunction & MF) const95 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
96 return requiresRegisterScavenging(MF);
97 }
98
99 bool
useFPForScavengingIndex(const MachineFunction & MF) const100 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
101 return false;
102 }
103
104 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const105 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
106 int SPAdj, unsigned FIOperandNum,
107 RegScavenger *RS) const {
108 assert(SPAdj == 0 && "Unexpected");
109 MachineInstr &MI = *II;
110 DebugLoc dl = MI.getDebugLoc();
111 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
112 int FrameIndex = FrameOp.getIndex();
113
114 MachineFunction &MF = *MI.getParent()->getParent();
115 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
116 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
117 int StackSize = MF.getFrameInfo()->getStackSize();
118
119 #ifndef NDEBUG
120 DEBUG(errs() << "\nFunction : "
121 << MF.getName() << "\n");
122 DEBUG(errs() << "<--------->\n");
123 DEBUG(MI.print(errs()));
124 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
125 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
126 DEBUG(errs() << "StackSize : " << StackSize << "\n");
127 #endif
128
129 Offset += StackSize;
130
131 unsigned FrameReg = getFrameRegister(MF);
132
133 // Special handling of DBG_VALUE instructions.
134 if (MI.isDebugValue()) {
135 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
136 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
137 return;
138 }
139
140 // fold constant into offset.
141 Offset += MI.getOperand(FIOperandNum + 1).getImm();
142 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
143
144 assert(Offset%4 == 0 && "Misaligned stack offset");
145
146 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
147
148 Offset/=4;
149
150 bool FP = TFI->hasFP(MF);
151
152 unsigned Reg = MI.getOperand(0).getReg();
153 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
154
155 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
156
157 MachineBasicBlock &MBB = *MI.getParent();
158
159 if (FP) {
160 bool isUs = isImmUs(Offset);
161
162 if (!isUs) {
163 if (!RS)
164 report_fatal_error("eliminateFrameIndex Frame size too big: " +
165 Twine(Offset));
166 unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II,
167 SPAdj);
168 loadConstant(MBB, II, ScratchReg, Offset, dl);
169 switch (MI.getOpcode()) {
170 case XCore::LDWFI:
171 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
172 .addReg(FrameReg)
173 .addReg(ScratchReg, RegState::Kill);
174 break;
175 case XCore::STWFI:
176 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
177 .addReg(Reg, getKillRegState(isKill))
178 .addReg(FrameReg)
179 .addReg(ScratchReg, RegState::Kill);
180 break;
181 case XCore::LDAWFI:
182 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
183 .addReg(FrameReg)
184 .addReg(ScratchReg, RegState::Kill);
185 break;
186 default:
187 llvm_unreachable("Unexpected Opcode");
188 }
189 } else {
190 switch (MI.getOpcode()) {
191 case XCore::LDWFI:
192 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
193 .addReg(FrameReg)
194 .addImm(Offset);
195 break;
196 case XCore::STWFI:
197 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
198 .addReg(Reg, getKillRegState(isKill))
199 .addReg(FrameReg)
200 .addImm(Offset);
201 break;
202 case XCore::LDAWFI:
203 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
204 .addReg(FrameReg)
205 .addImm(Offset);
206 break;
207 default:
208 llvm_unreachable("Unexpected Opcode");
209 }
210 }
211 } else {
212 bool isU6 = isImmU6(Offset);
213 if (!isU6 && !isImmU16(Offset))
214 report_fatal_error("eliminateFrameIndex Frame size too big: " +
215 Twine(Offset));
216
217 switch (MI.getOpcode()) {
218 int NewOpcode;
219 case XCore::LDWFI:
220 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
221 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
222 .addImm(Offset);
223 break;
224 case XCore::STWFI:
225 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
226 BuildMI(MBB, II, dl, TII.get(NewOpcode))
227 .addReg(Reg, getKillRegState(isKill))
228 .addImm(Offset);
229 break;
230 case XCore::LDAWFI:
231 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
232 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
233 .addImm(Offset);
234 break;
235 default:
236 llvm_unreachable("Unexpected Opcode");
237 }
238 }
239 // Erase old instruction.
240 MBB.erase(II);
241 }
242
243 void XCoreRegisterInfo::
loadConstant(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DstReg,int64_t Value,DebugLoc dl) const244 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
245 unsigned DstReg, int64_t Value, DebugLoc dl) const {
246 // TODO use mkmsk if possible.
247 if (!isImmU16(Value)) {
248 // TODO use constant pool.
249 report_fatal_error("loadConstant value too big " + Twine(Value));
250 }
251 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
252 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
253 }
254
getFrameRegister(const MachineFunction & MF) const255 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
256 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
257
258 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
259 }
260