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Searched refs:isPPC64 (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h74 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { in getReturnSaveOffset() argument
76 return isPPC64 ? 16 : 8; in getReturnSaveOffset()
78 return isPPC64 ? 16 : 4; in getReturnSaveOffset()
83 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { in getFramePointerSaveOffset() argument
90 return isPPC64 ? -8U : -4U; in getFramePointerSaveOffset()
93 return isPPC64 ? -8U : -4U; in getFramePointerSaveOffset()
98 static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) { in getLinkageSize() argument
99 if (isDarwinABI || isPPC64) in getLinkageSize()
100 return 6 * (isPPC64 ? 8 : 4); in getLinkageSize()
108 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) { in getMinCallArgumentsSize() argument
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DPPCFrameLowering.cpp228 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- in determineFrameLayout()
234 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. in determineFrameLayout()
248 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), in determineFrameLayout()
336 bool isPPC64 = Subtarget.isPPC64(); in emitPrologue() local
345 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); in emitPrologue()
355 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); in emitPrologue()
359 if (isPPC64) { in emitPrologue()
402 if (!isPPC64) { in emitPrologue()
487 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); in emitPrologue()
493 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); in emitPrologue()
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DPPCRegisterInfo.cpp53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
54 ST.isPPC64() ? 0 : 1, in PPCRegisterInfo()
55 ST.isPPC64() ? 0 : 1), in PPCRegisterInfo()
79 if (Subtarget.isPPC64()) in getPointerRegClass()
87 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : in getCalleeSavedRegs()
90 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; in getCalleeSavedRegs()
96 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : in getCallPreservedMask()
99 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; in getCallPreservedMask()
122 if (Subtarget.isPPC64()) { in getReservedRegs()
188 bool LP64 = Subtarget.isPPC64(); in lowerDynamicAlloc()
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DPPCInstr64Bit.td451 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
453 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
455 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
457 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
461 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
464 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
468 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
480 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
484 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
487 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
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DPPCAsmPrinter.cpp534 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
567 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
583 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
599 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
619 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
635 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
651 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
671 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
687 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); in EmitInstruction()
706 OutStreamer.EmitInstruction(MCInstBuilder(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR) in EmitInstruction()
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DPPCCTRLoops.cpp676 bool isPPC64 = Subtarget.isPPC64(); in convertToCTRLoop() local
680 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; in convertToCTRLoop()
688 unsigned CopyOp = (isPPC64 && SrcRC == GPRC) ? in convertToCTRLoop()
697 TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG), in convertToCTRLoop()
711 TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), in convertToCTRLoop()
716 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), in convertToCTRLoop()
720 TII->get(isPPC64 ? PPC::LI8 : PPC::LI), in convertToCTRLoop()
727 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg, in convertToCTRLoop()
744 MBB->addLiveIn(isPPC64 ? PPC::CTR8 : PPC::CTR); in convertToCTRLoop()
758 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in convertToCTRLoop()
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DPPCSubtarget.h122 if (isPPC64() && isSVR4ABI()) { in getDataLayoutString()
129 return isPPC64() ? "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64" in getDataLayoutString()
135 bool isPPC64() const { return IsPPC64; } in isPPC64() function
DPPCInstrInfo.cpp212 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); in AnalyzeBranch() local
253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
302 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in AnalyzeBranch()
380 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); in InsertBranch() local
388 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in InsertBranch()
389 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in InsertBranch()
399 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in InsertBranch()
400 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in InsertBranch()
DPPCISelLowering.cpp82 bool isPPC64 = Subtarget->isPPC64(); in PPCTargetLowering() local
83 setMinStackArgumentAlignment(isPPC64 ? 8:4); in PPCTargetLowering()
239 if (isPPC64) { in PPCTargetLowering()
457 if (isPPC64) { in PPCTargetLowering()
491 if (isPPC64 && Subtarget->isJITCodeModel()) in PPCTargetLowering()
532 if (PPCSubTarget.isPPC64()) in getByValTypeAlignment()
1034 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImm()
1083 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegRegOnly()
1146 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImmShift()
1297 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { in LowerConstantPool()
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DPPCSubtarget.cpp139 if (isPPC64()) in enablePostRAScheduler()
DPPCISelDAGToDAG.cpp723 bool isPPC64 = (PtrVT == MVT::i64); in SelectSETCC() local
739 if (isPPC64) break; in SelectSETCC()
763 if (isPPC64) break; in SelectSETCC()
772 if (isPPC64) break; in SelectSETCC()
1213 bool isPPC64 = (PtrVT == MVT::i64); in Select() local
1216 if (!isPPC64) in Select()
1282 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); in Select()
1413 if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64()) in PostprocessISelDAG()
DPPCTargetTransformInfo.cpp143 if (ST->isPPC64()) in getRegisterBitWidth()
DPPCCallingConv.td26 CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
DPPCISelLowering.h559 unsigned MinReservedArea, bool isPPC64) const;
DPPCInstrFormats.td18 bit PPC64 = 0; // Default value, override with isPPC64
62 bit PPC64 = 0; // Default value, override with isPPC64
DPPCInstrInfo.td317 class isPPC64 { bit PPC64 = 1; }
413 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
414 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCTargetDesc.cpp45 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64); in createPPCMCRegisterInfo() local
46 unsigned Flavour = isPPC64 ? 0 : 1; in createPPCMCRegisterInfo()
47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; in createPPCMCRegisterInfo()
63 bool isPPC64 = TheTriple.getArch() == Triple::ppc64; in createPPCMCAsmInfo() local
67 MAI = new PPCMCAsmInfoDarwin(isPPC64); in createPPCMCAsmInfo()
69 MAI = new PPCLinuxMCAsmInfo(isPPC64); in createPPCMCAsmInfo()
73 MachineLocation Src(isPPC64? PPC::X1 : PPC::R1, 0); in createPPCMCAsmInfo()