1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCISelLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
37 using namespace llvm;
38
39 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
42 CCState &State);
43 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
44 MVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
47 CCState &State);
48 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
49 MVT &LocVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
52 CCState &State);
53
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
56
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
59
60 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
61 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
62
CreateTLOF(const PPCTargetMachine & TM)63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
64 if (TM.getSubtargetImpl()->isDarwin())
65 return new TargetLoweringObjectFileMachO();
66
67 return new TargetLoweringObjectFileELF();
68 }
69
PPCTargetLowering(PPCTargetMachine & TM)70 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73
74 setPow2DivIsCheap();
75
76 // Use _setjmp/_longjmp instead of setjmp/longjmp.
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(true);
79
80 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
81 // arguments are at least 4/8 bytes aligned.
82 bool isPPC64 = Subtarget->isPPC64();
83 setMinStackArgumentAlignment(isPPC64 ? 8:4);
84
85 // Set up the register classes.
86 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
87 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
88 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
89
90 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
93
94 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
95
96 // PowerPC has pre-inc load and store's.
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
107
108 // This is used in the ppcf128->int sequence. Note it has different semantics
109 // from FP_ROUND: that rounds to nearest, this rounds to zero.
110 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
111
112 // We do not currently implement these libm ops for PowerPC.
113 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
114 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
115 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
116 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
117 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
118
119 // PowerPC has no SREM/UREM instructions
120 setOperationAction(ISD::SREM, MVT::i32, Expand);
121 setOperationAction(ISD::UREM, MVT::i32, Expand);
122 setOperationAction(ISD::SREM, MVT::i64, Expand);
123 setOperationAction(ISD::UREM, MVT::i64, Expand);
124
125 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
126 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
127 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
128 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
129 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
130 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
131 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
132 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
133 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
134
135 // We don't support sin/cos/sqrt/fmod/pow
136 setOperationAction(ISD::FSIN , MVT::f64, Expand);
137 setOperationAction(ISD::FCOS , MVT::f64, Expand);
138 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
139 setOperationAction(ISD::FREM , MVT::f64, Expand);
140 setOperationAction(ISD::FPOW , MVT::f64, Expand);
141 setOperationAction(ISD::FMA , MVT::f64, Legal);
142 setOperationAction(ISD::FSIN , MVT::f32, Expand);
143 setOperationAction(ISD::FCOS , MVT::f32, Expand);
144 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
145 setOperationAction(ISD::FREM , MVT::f32, Expand);
146 setOperationAction(ISD::FPOW , MVT::f32, Expand);
147 setOperationAction(ISD::FMA , MVT::f32, Legal);
148
149 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
150
151 // If we're enabling GP optimizations, use hardware square root
152 if (!Subtarget->hasFSQRT()) {
153 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
154 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
155 }
156
157 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
158 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
159
160 // PowerPC does not have BSWAP, CTPOP or CTTZ
161 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
162 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
163 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
166 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
167 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
168 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
169 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
171
172 // PowerPC does not have ROTR
173 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
174 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
175
176 // PowerPC does not have Select
177 setOperationAction(ISD::SELECT, MVT::i32, Expand);
178 setOperationAction(ISD::SELECT, MVT::i64, Expand);
179 setOperationAction(ISD::SELECT, MVT::f32, Expand);
180 setOperationAction(ISD::SELECT, MVT::f64, Expand);
181
182 // PowerPC wants to turn select_cc of FP into fsel when possible.
183 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
184 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
185
186 // PowerPC wants to optimize integer setcc a bit
187 setOperationAction(ISD::SETCC, MVT::i32, Custom);
188
189 // PowerPC does not have BRCOND which requires SetCC
190 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
191
192 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
193
194 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
195 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
196
197 // PowerPC does not have [U|S]INT_TO_FP
198 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
199 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
200
201 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
202 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
203 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
204 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
205
206 // We cannot sextinreg(i1). Expand to shifts.
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
208
209 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
210 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
211 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
212 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
213
214
215 // We want to legalize GlobalAddress and ConstantPool nodes into the
216 // appropriate instructions to materialize the address.
217 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
218 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
219 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
220 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
221 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
222 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
223 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
224 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
225 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
226 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
227
228 // TRAP is legal.
229 setOperationAction(ISD::TRAP, MVT::Other, Legal);
230
231 // TRAMPOLINE is custom lowered.
232 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
233 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
234
235 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
236 setOperationAction(ISD::VASTART , MVT::Other, Custom);
237
238 if (Subtarget->isSVR4ABI()) {
239 if (isPPC64) {
240 // VAARG always uses double-word chunks, so promote anything smaller.
241 setOperationAction(ISD::VAARG, MVT::i1, Promote);
242 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
243 setOperationAction(ISD::VAARG, MVT::i8, Promote);
244 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
245 setOperationAction(ISD::VAARG, MVT::i16, Promote);
246 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
247 setOperationAction(ISD::VAARG, MVT::i32, Promote);
248 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
249 setOperationAction(ISD::VAARG, MVT::Other, Expand);
250 } else {
251 // VAARG is custom lowered with the 32-bit SVR4 ABI.
252 setOperationAction(ISD::VAARG, MVT::Other, Custom);
253 setOperationAction(ISD::VAARG, MVT::i64, Custom);
254 }
255 } else
256 setOperationAction(ISD::VAARG, MVT::Other, Expand);
257
258 // Use the default implementation.
259 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
260 setOperationAction(ISD::VAEND , MVT::Other, Expand);
261 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
262 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
263 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
264 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
265
266 // We want to custom lower some of our intrinsics.
267 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
268
269 // Comparisons that require checking two conditions.
270 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
271 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
272 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
273 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
274 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
275 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
276 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
277 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
278 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
279 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
280 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
281 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
282
283 if (Subtarget->has64BitSupport()) {
284 // They also have instructions for converting between i64 and fp.
285 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
286 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
287 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
289 // This is just the low 32 bits of a (signed) fp->i64 conversion.
290 // We cannot do this with Promote because i64 is not a legal type.
291 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
292
293 // FIXME: disable this lowered code. This generates 64-bit register values,
294 // and we don't model the fact that the top part is clobbered by calls. We
295 // need to flag these together so that the value isn't live across a call.
296 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
297 } else {
298 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
299 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
300 }
301
302 if (Subtarget->use64BitRegs()) {
303 // 64-bit PowerPC implementations can support i64 types directly
304 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
305 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
306 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
307 // 64-bit PowerPC wants to expand i128 shifts itself.
308 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
309 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
310 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
311 } else {
312 // 32-bit PowerPC wants to expand i64 shifts itself.
313 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
314 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
315 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
316 }
317
318 if (Subtarget->hasAltivec()) {
319 // First set operation action for all vector types to expand. Then we
320 // will selectively turn on ones that can be effectively codegen'd.
321 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
322 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
323 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
324
325 // add/sub are legal for all supported vector VT's.
326 setOperationAction(ISD::ADD , VT, Legal);
327 setOperationAction(ISD::SUB , VT, Legal);
328
329 // We promote all shuffles to v16i8.
330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
331 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
332
333 // We promote all non-typed operations to v4i32.
334 setOperationAction(ISD::AND , VT, Promote);
335 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
336 setOperationAction(ISD::OR , VT, Promote);
337 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
338 setOperationAction(ISD::XOR , VT, Promote);
339 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
340 setOperationAction(ISD::LOAD , VT, Promote);
341 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
342 setOperationAction(ISD::SELECT, VT, Promote);
343 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
344 setOperationAction(ISD::STORE, VT, Promote);
345 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
346
347 // No other operations are legal.
348 setOperationAction(ISD::MUL , VT, Expand);
349 setOperationAction(ISD::SDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UDIV, VT, Expand);
352 setOperationAction(ISD::UREM, VT, Expand);
353 setOperationAction(ISD::FDIV, VT, Expand);
354 setOperationAction(ISD::FNEG, VT, Expand);
355 setOperationAction(ISD::FSQRT, VT, Expand);
356 setOperationAction(ISD::FLOG, VT, Expand);
357 setOperationAction(ISD::FLOG10, VT, Expand);
358 setOperationAction(ISD::FLOG2, VT, Expand);
359 setOperationAction(ISD::FEXP, VT, Expand);
360 setOperationAction(ISD::FEXP2, VT, Expand);
361 setOperationAction(ISD::FSIN, VT, Expand);
362 setOperationAction(ISD::FCOS, VT, Expand);
363 setOperationAction(ISD::FABS, VT, Expand);
364 setOperationAction(ISD::FPOWI, VT, Expand);
365 setOperationAction(ISD::FFLOOR, VT, Expand);
366 setOperationAction(ISD::FCEIL, VT, Expand);
367 setOperationAction(ISD::FTRUNC, VT, Expand);
368 setOperationAction(ISD::FRINT, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, VT, Expand);
370 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
371 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
372 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
373 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
374 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
375 setOperationAction(ISD::UDIVREM, VT, Expand);
376 setOperationAction(ISD::SDIVREM, VT, Expand);
377 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
378 setOperationAction(ISD::FPOW, VT, Expand);
379 setOperationAction(ISD::CTPOP, VT, Expand);
380 setOperationAction(ISD::CTLZ, VT, Expand);
381 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
382 setOperationAction(ISD::CTTZ, VT, Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
384 setOperationAction(ISD::VSELECT, VT, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
386
387 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
388 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
389 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
390 setTruncStoreAction(VT, InnerVT, Expand);
391 }
392 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
393 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
394 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
395 }
396
397 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
398 // with merges, splats, etc.
399 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
400
401 setOperationAction(ISD::AND , MVT::v4i32, Legal);
402 setOperationAction(ISD::OR , MVT::v4i32, Legal);
403 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
404 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
405 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
406 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
407 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
411 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
412 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
413 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
414 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
415
416 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
417 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
418 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
419 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
420
421 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
422 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
423 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
424 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
425 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
426
427 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
428 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
429
430 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
431 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
432 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
433 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
434
435 // Altivec does not contain unordered floating-point compare instructions
436 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
437 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
438 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
439 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
440 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
441 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
442 }
443
444 if (Subtarget->has64BitSupport()) {
445 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
446 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
447 }
448
449 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
450 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
451 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
452 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
453
454 setBooleanContents(ZeroOrOneBooleanContent);
455 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
456
457 if (isPPC64) {
458 setStackPointerRegisterToSaveRestore(PPC::X1);
459 setExceptionPointerRegister(PPC::X3);
460 setExceptionSelectorRegister(PPC::X4);
461 } else {
462 setStackPointerRegisterToSaveRestore(PPC::R1);
463 setExceptionPointerRegister(PPC::R3);
464 setExceptionSelectorRegister(PPC::R4);
465 }
466
467 // We have target-specific dag combine patterns for the following nodes:
468 setTargetDAGCombine(ISD::SINT_TO_FP);
469 setTargetDAGCombine(ISD::STORE);
470 setTargetDAGCombine(ISD::BR_CC);
471 setTargetDAGCombine(ISD::BSWAP);
472
473 // Darwin long double math library functions have $LDBL128 appended.
474 if (Subtarget->isDarwin()) {
475 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
476 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
477 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
478 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
479 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
480 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
481 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
482 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
483 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
484 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
485 }
486
487 setMinFunctionAlignment(2);
488 if (PPCSubTarget.isDarwin())
489 setPrefFunctionAlignment(4);
490
491 if (isPPC64 && Subtarget->isJITCodeModel())
492 // Temporary workaround for the inability of PPC64 JIT to handle jump
493 // tables.
494 setSupportJumpTables(false);
495
496 setInsertFencesForAtomic(true);
497
498 setSchedulingPreference(Sched::Hybrid);
499
500 computeRegisterProperties();
501
502 // The Freescale cores does better with aggressive inlining of memcpy and
503 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
504 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
505 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
506 MaxStoresPerMemset = 32;
507 MaxStoresPerMemsetOptSize = 16;
508 MaxStoresPerMemcpy = 32;
509 MaxStoresPerMemcpyOptSize = 8;
510 MaxStoresPerMemmove = 32;
511 MaxStoresPerMemmoveOptSize = 8;
512
513 setPrefFunctionAlignment(4);
514 BenefitFromCodePlacementOpt = true;
515 }
516 }
517
518 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
519 /// function arguments in the caller parameter area.
getByValTypeAlignment(Type * Ty) const520 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
521 const TargetMachine &TM = getTargetMachine();
522 // Darwin passes everything on 4 byte boundary.
523 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
524 return 4;
525
526 // 16byte and wider vectors are passed on 16byte boundary.
527 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
528 if (VTy->getBitWidth() >= 128)
529 return 16;
530
531 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
532 if (PPCSubTarget.isPPC64())
533 return 8;
534
535 return 4;
536 }
537
getTargetNodeName(unsigned Opcode) const538 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
539 switch (Opcode) {
540 default: return 0;
541 case PPCISD::FSEL: return "PPCISD::FSEL";
542 case PPCISD::FCFID: return "PPCISD::FCFID";
543 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
544 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
545 case PPCISD::STFIWX: return "PPCISD::STFIWX";
546 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
547 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
548 case PPCISD::VPERM: return "PPCISD::VPERM";
549 case PPCISD::Hi: return "PPCISD::Hi";
550 case PPCISD::Lo: return "PPCISD::Lo";
551 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
552 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
553 case PPCISD::LOAD: return "PPCISD::LOAD";
554 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
555 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
556 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
557 case PPCISD::SRL: return "PPCISD::SRL";
558 case PPCISD::SRA: return "PPCISD::SRA";
559 case PPCISD::SHL: return "PPCISD::SHL";
560 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
561 case PPCISD::STD_32: return "PPCISD::STD_32";
562 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
563 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4";
564 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
565 case PPCISD::NOP: return "PPCISD::NOP";
566 case PPCISD::MTCTR: return "PPCISD::MTCTR";
567 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
568 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
569 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
570 case PPCISD::MFCR: return "PPCISD::MFCR";
571 case PPCISD::VCMP: return "PPCISD::VCMP";
572 case PPCISD::VCMPo: return "PPCISD::VCMPo";
573 case PPCISD::LBRX: return "PPCISD::LBRX";
574 case PPCISD::STBRX: return "PPCISD::STBRX";
575 case PPCISD::LARX: return "PPCISD::LARX";
576 case PPCISD::STCX: return "PPCISD::STCX";
577 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
578 case PPCISD::MFFS: return "PPCISD::MFFS";
579 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
580 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
581 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
582 case PPCISD::MTFSF: return "PPCISD::MTFSF";
583 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
584 case PPCISD::CR6SET: return "PPCISD::CR6SET";
585 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
586 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
587 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
588 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
589 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
590 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
591 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
592 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
593 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
594 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
595 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
596 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
597 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
598 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
599 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
600 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
601 }
602 }
603
getSetCCResultType(EVT VT) const604 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
605 if (!VT.isVector())
606 return MVT::i32;
607 return VT.changeVectorElementTypeToInteger();
608 }
609
610 //===----------------------------------------------------------------------===//
611 // Node matching predicates, for use by the tblgen matching code.
612 //===----------------------------------------------------------------------===//
613
614 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
isFloatingPointZero(SDValue Op)615 static bool isFloatingPointZero(SDValue Op) {
616 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
617 return CFP->getValueAPF().isZero();
618 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
619 // Maybe this has already been legalized into the constant pool?
620 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
621 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
622 return CFP->getValueAPF().isZero();
623 }
624 return false;
625 }
626
627 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
628 /// true if Op is undef or if it matches the specified value.
isConstantOrUndef(int Op,int Val)629 static bool isConstantOrUndef(int Op, int Val) {
630 return Op < 0 || Op == Val;
631 }
632
633 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
634 /// VPKUHUM instruction.
isVPKUHUMShuffleMask(ShuffleVectorSDNode * N,bool isUnary)635 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
636 if (!isUnary) {
637 for (unsigned i = 0; i != 16; ++i)
638 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
639 return false;
640 } else {
641 for (unsigned i = 0; i != 8; ++i)
642 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
643 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
644 return false;
645 }
646 return true;
647 }
648
649 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
650 /// VPKUWUM instruction.
isVPKUWUMShuffleMask(ShuffleVectorSDNode * N,bool isUnary)651 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
652 if (!isUnary) {
653 for (unsigned i = 0; i != 16; i += 2)
654 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
655 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
656 return false;
657 } else {
658 for (unsigned i = 0; i != 8; i += 2)
659 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
660 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
661 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
662 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
663 return false;
664 }
665 return true;
666 }
667
668 /// isVMerge - Common function, used to match vmrg* shuffles.
669 ///
isVMerge(ShuffleVectorSDNode * N,unsigned UnitSize,unsigned LHSStart,unsigned RHSStart)670 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
671 unsigned LHSStart, unsigned RHSStart) {
672 assert(N->getValueType(0) == MVT::v16i8 &&
673 "PPC only supports shuffles by bytes!");
674 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
675 "Unsupported merge size!");
676
677 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
678 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
679 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
680 LHSStart+j+i*UnitSize) ||
681 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
682 RHSStart+j+i*UnitSize))
683 return false;
684 }
685 return true;
686 }
687
688 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
689 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGLShuffleMask(ShuffleVectorSDNode * N,unsigned UnitSize,bool isUnary)690 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
691 bool isUnary) {
692 if (!isUnary)
693 return isVMerge(N, UnitSize, 8, 24);
694 return isVMerge(N, UnitSize, 8, 8);
695 }
696
697 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
698 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGHShuffleMask(ShuffleVectorSDNode * N,unsigned UnitSize,bool isUnary)699 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
700 bool isUnary) {
701 if (!isUnary)
702 return isVMerge(N, UnitSize, 0, 16);
703 return isVMerge(N, UnitSize, 0, 0);
704 }
705
706
707 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
708 /// amount, otherwise return -1.
isVSLDOIShuffleMask(SDNode * N,bool isUnary)709 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
710 assert(N->getValueType(0) == MVT::v16i8 &&
711 "PPC only supports shuffles by bytes!");
712
713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
714
715 // Find the first non-undef value in the shuffle mask.
716 unsigned i;
717 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
718 /*search*/;
719
720 if (i == 16) return -1; // all undef.
721
722 // Otherwise, check to see if the rest of the elements are consecutively
723 // numbered from this value.
724 unsigned ShiftAmt = SVOp->getMaskElt(i);
725 if (ShiftAmt < i) return -1;
726 ShiftAmt -= i;
727
728 if (!isUnary) {
729 // Check the rest of the elements to see if they are consecutive.
730 for (++i; i != 16; ++i)
731 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
732 return -1;
733 } else {
734 // Check the rest of the elements to see if they are consecutive.
735 for (++i; i != 16; ++i)
736 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
737 return -1;
738 }
739 return ShiftAmt;
740 }
741
742 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
743 /// specifies a splat of a single element that is suitable for input to
744 /// VSPLTB/VSPLTH/VSPLTW.
isSplatShuffleMask(ShuffleVectorSDNode * N,unsigned EltSize)745 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
746 assert(N->getValueType(0) == MVT::v16i8 &&
747 (EltSize == 1 || EltSize == 2 || EltSize == 4));
748
749 // This is a splat operation if each element of the permute is the same, and
750 // if the value doesn't reference the second vector.
751 unsigned ElementBase = N->getMaskElt(0);
752
753 // FIXME: Handle UNDEF elements too!
754 if (ElementBase >= 16)
755 return false;
756
757 // Check that the indices are consecutive, in the case of a multi-byte element
758 // splatted with a v16i8 mask.
759 for (unsigned i = 1; i != EltSize; ++i)
760 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
761 return false;
762
763 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
764 if (N->getMaskElt(i) < 0) continue;
765 for (unsigned j = 0; j != EltSize; ++j)
766 if (N->getMaskElt(i+j) != N->getMaskElt(j))
767 return false;
768 }
769 return true;
770 }
771
772 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
773 /// are -0.0.
isAllNegativeZeroVector(SDNode * N)774 bool PPC::isAllNegativeZeroVector(SDNode *N) {
775 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
776
777 APInt APVal, APUndef;
778 unsigned BitSize;
779 bool HasAnyUndefs;
780
781 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
782 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
783 return CFP->getValueAPF().isNegZero();
784
785 return false;
786 }
787
788 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
789 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
getVSPLTImmediate(SDNode * N,unsigned EltSize)790 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
792 assert(isSplatShuffleMask(SVOp, EltSize));
793 return SVOp->getMaskElt(0) / EltSize;
794 }
795
796 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
797 /// by using a vspltis[bhw] instruction of the specified element size, return
798 /// the constant being splatted. The ByteSize field indicates the number of
799 /// bytes of each element [124] -> [bhw].
get_VSPLTI_elt(SDNode * N,unsigned ByteSize,SelectionDAG & DAG)800 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
801 SDValue OpVal(0, 0);
802
803 // If ByteSize of the splat is bigger than the element size of the
804 // build_vector, then we have a case where we are checking for a splat where
805 // multiple elements of the buildvector are folded together into a single
806 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
807 unsigned EltSize = 16/N->getNumOperands();
808 if (EltSize < ByteSize) {
809 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
810 SDValue UniquedVals[4];
811 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
812
813 // See if all of the elements in the buildvector agree across.
814 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
815 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
816 // If the element isn't a constant, bail fully out.
817 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
818
819
820 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
821 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
822 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
823 return SDValue(); // no match.
824 }
825
826 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
827 // either constant or undef values that are identical for each chunk. See
828 // if these chunks can form into a larger vspltis*.
829
830 // Check to see if all of the leading entries are either 0 or -1. If
831 // neither, then this won't fit into the immediate field.
832 bool LeadingZero = true;
833 bool LeadingOnes = true;
834 for (unsigned i = 0; i != Multiple-1; ++i) {
835 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
836
837 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
838 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
839 }
840 // Finally, check the least significant entry.
841 if (LeadingZero) {
842 if (UniquedVals[Multiple-1].getNode() == 0)
843 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
844 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
845 if (Val < 16)
846 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
847 }
848 if (LeadingOnes) {
849 if (UniquedVals[Multiple-1].getNode() == 0)
850 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
851 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
852 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
853 return DAG.getTargetConstant(Val, MVT::i32);
854 }
855
856 return SDValue();
857 }
858
859 // Check to see if this buildvec has a single non-undef value in its elements.
860 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
861 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
862 if (OpVal.getNode() == 0)
863 OpVal = N->getOperand(i);
864 else if (OpVal != N->getOperand(i))
865 return SDValue();
866 }
867
868 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
869
870 unsigned ValSizeInBytes = EltSize;
871 uint64_t Value = 0;
872 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
873 Value = CN->getZExtValue();
874 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
875 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
876 Value = FloatToBits(CN->getValueAPF().convertToFloat());
877 }
878
879 // If the splat value is larger than the element value, then we can never do
880 // this splat. The only case that we could fit the replicated bits into our
881 // immediate field for would be zero, and we prefer to use vxor for it.
882 if (ValSizeInBytes < ByteSize) return SDValue();
883
884 // If the element value is larger than the splat value, cut it in half and
885 // check to see if the two halves are equal. Continue doing this until we
886 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
887 while (ValSizeInBytes > ByteSize) {
888 ValSizeInBytes >>= 1;
889
890 // If the top half equals the bottom half, we're still ok.
891 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
892 (Value & ((1 << (8*ValSizeInBytes))-1)))
893 return SDValue();
894 }
895
896 // Properly sign extend the value.
897 int MaskVal = SignExtend32(Value, ByteSize * 8);
898
899 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
900 if (MaskVal == 0) return SDValue();
901
902 // Finally, if this value fits in a 5 bit sext field, return it
903 if (SignExtend32<5>(MaskVal) == MaskVal)
904 return DAG.getTargetConstant(MaskVal, MVT::i32);
905 return SDValue();
906 }
907
908 //===----------------------------------------------------------------------===//
909 // Addressing Mode Selection
910 //===----------------------------------------------------------------------===//
911
912 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
913 /// or 64-bit immediate, and if the value can be accurately represented as a
914 /// sign extension from a 16-bit value. If so, this returns true and the
915 /// immediate.
isIntS16Immediate(SDNode * N,short & Imm)916 static bool isIntS16Immediate(SDNode *N, short &Imm) {
917 if (N->getOpcode() != ISD::Constant)
918 return false;
919
920 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
921 if (N->getValueType(0) == MVT::i32)
922 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
923 else
924 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
925 }
isIntS16Immediate(SDValue Op,short & Imm)926 static bool isIntS16Immediate(SDValue Op, short &Imm) {
927 return isIntS16Immediate(Op.getNode(), Imm);
928 }
929
930
931 /// SelectAddressRegReg - Given the specified addressed, check to see if it
932 /// can be represented as an indexed [r+r] operation. Returns false if it
933 /// can be more efficiently represented with [r+imm].
SelectAddressRegReg(SDValue N,SDValue & Base,SDValue & Index,SelectionDAG & DAG) const934 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
935 SDValue &Index,
936 SelectionDAG &DAG) const {
937 short imm = 0;
938 if (N.getOpcode() == ISD::ADD) {
939 if (isIntS16Immediate(N.getOperand(1), imm))
940 return false; // r+i
941 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
942 return false; // r+i
943
944 Base = N.getOperand(0);
945 Index = N.getOperand(1);
946 return true;
947 } else if (N.getOpcode() == ISD::OR) {
948 if (isIntS16Immediate(N.getOperand(1), imm))
949 return false; // r+i can fold it if we can.
950
951 // If this is an or of disjoint bitfields, we can codegen this as an add
952 // (for better address arithmetic) if the LHS and RHS of the OR are provably
953 // disjoint.
954 APInt LHSKnownZero, LHSKnownOne;
955 APInt RHSKnownZero, RHSKnownOne;
956 DAG.ComputeMaskedBits(N.getOperand(0),
957 LHSKnownZero, LHSKnownOne);
958
959 if (LHSKnownZero.getBoolValue()) {
960 DAG.ComputeMaskedBits(N.getOperand(1),
961 RHSKnownZero, RHSKnownOne);
962 // If all of the bits are known zero on the LHS or RHS, the add won't
963 // carry.
964 if (~(LHSKnownZero | RHSKnownZero) == 0) {
965 Base = N.getOperand(0);
966 Index = N.getOperand(1);
967 return true;
968 }
969 }
970 }
971
972 return false;
973 }
974
975 /// Returns true if the address N can be represented by a base register plus
976 /// a signed 16-bit displacement [r+imm], and if it is not better
977 /// represented as reg+reg.
SelectAddressRegImm(SDValue N,SDValue & Disp,SDValue & Base,SelectionDAG & DAG) const978 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
979 SDValue &Base,
980 SelectionDAG &DAG) const {
981 // FIXME dl should come from parent load or store, not from address
982 DebugLoc dl = N.getDebugLoc();
983 // If this can be more profitably realized as r+r, fail.
984 if (SelectAddressRegReg(N, Disp, Base, DAG))
985 return false;
986
987 if (N.getOpcode() == ISD::ADD) {
988 short imm = 0;
989 if (isIntS16Immediate(N.getOperand(1), imm)) {
990 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
991 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
992 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
993 } else {
994 Base = N.getOperand(0);
995 }
996 return true; // [r+i]
997 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
998 // Match LOAD (ADD (X, Lo(G))).
999 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1000 && "Cannot handle constant offsets yet!");
1001 Disp = N.getOperand(1).getOperand(0); // The global address.
1002 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1003 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1004 Disp.getOpcode() == ISD::TargetConstantPool ||
1005 Disp.getOpcode() == ISD::TargetJumpTable);
1006 Base = N.getOperand(0);
1007 return true; // [&g+r]
1008 }
1009 } else if (N.getOpcode() == ISD::OR) {
1010 short imm = 0;
1011 if (isIntS16Immediate(N.getOperand(1), imm)) {
1012 // If this is an or of disjoint bitfields, we can codegen this as an add
1013 // (for better address arithmetic) if the LHS and RHS of the OR are
1014 // provably disjoint.
1015 APInt LHSKnownZero, LHSKnownOne;
1016 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1017
1018 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1019 // If all of the bits are known zero on the LHS or RHS, the add won't
1020 // carry.
1021 Base = N.getOperand(0);
1022 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1023 return true;
1024 }
1025 }
1026 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1027 // Loading from a constant address.
1028
1029 // If this address fits entirely in a 16-bit sext immediate field, codegen
1030 // this as "d, 0"
1031 short Imm;
1032 if (isIntS16Immediate(CN, Imm)) {
1033 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1034 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1035 CN->getValueType(0));
1036 return true;
1037 }
1038
1039 // Handle 32-bit sext immediates with LIS + addr mode.
1040 if (CN->getValueType(0) == MVT::i32 ||
1041 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1042 int Addr = (int)CN->getZExtValue();
1043
1044 // Otherwise, break this down into an LIS + disp.
1045 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1046
1047 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1048 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1049 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1050 return true;
1051 }
1052 }
1053
1054 Disp = DAG.getTargetConstant(0, getPointerTy());
1055 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1056 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1057 else
1058 Base = N;
1059 return true; // [r+0]
1060 }
1061
1062 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1063 /// represented as an indexed [r+r] operation.
SelectAddressRegRegOnly(SDValue N,SDValue & Base,SDValue & Index,SelectionDAG & DAG) const1064 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1065 SDValue &Index,
1066 SelectionDAG &DAG) const {
1067 // Check to see if we can easily represent this as an [r+r] address. This
1068 // will fail if it thinks that the address is more profitably represented as
1069 // reg+imm, e.g. where imm = 0.
1070 if (SelectAddressRegReg(N, Base, Index, DAG))
1071 return true;
1072
1073 // If the operand is an addition, always emit this as [r+r], since this is
1074 // better (for code size, and execution, as the memop does the add for free)
1075 // than emitting an explicit add.
1076 if (N.getOpcode() == ISD::ADD) {
1077 Base = N.getOperand(0);
1078 Index = N.getOperand(1);
1079 return true;
1080 }
1081
1082 // Otherwise, do it the hard way, using R0 as the base register.
1083 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1084 N.getValueType());
1085 Index = N;
1086 return true;
1087 }
1088
1089 /// SelectAddressRegImmShift - Returns true if the address N can be
1090 /// represented by a base register plus a signed 14-bit displacement
1091 /// [r+imm*4]. Suitable for use by STD and friends.
SelectAddressRegImmShift(SDValue N,SDValue & Disp,SDValue & Base,SelectionDAG & DAG) const1092 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1093 SDValue &Base,
1094 SelectionDAG &DAG) const {
1095 // FIXME dl should come from the parent load or store, not the address
1096 DebugLoc dl = N.getDebugLoc();
1097 // If this can be more profitably realized as r+r, fail.
1098 if (SelectAddressRegReg(N, Disp, Base, DAG))
1099 return false;
1100
1101 if (N.getOpcode() == ISD::ADD) {
1102 short imm = 0;
1103 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1104 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1105 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1106 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1107 } else {
1108 Base = N.getOperand(0);
1109 }
1110 return true; // [r+i]
1111 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1112 // Match LOAD (ADD (X, Lo(G))).
1113 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1114 && "Cannot handle constant offsets yet!");
1115 Disp = N.getOperand(1).getOperand(0); // The global address.
1116 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1117 Disp.getOpcode() == ISD::TargetConstantPool ||
1118 Disp.getOpcode() == ISD::TargetJumpTable);
1119 Base = N.getOperand(0);
1120 return true; // [&g+r]
1121 }
1122 } else if (N.getOpcode() == ISD::OR) {
1123 short imm = 0;
1124 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1125 // If this is an or of disjoint bitfields, we can codegen this as an add
1126 // (for better address arithmetic) if the LHS and RHS of the OR are
1127 // provably disjoint.
1128 APInt LHSKnownZero, LHSKnownOne;
1129 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1130 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1131 // If all of the bits are known zero on the LHS or RHS, the add won't
1132 // carry.
1133 Base = N.getOperand(0);
1134 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1135 return true;
1136 }
1137 }
1138 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1139 // Loading from a constant address. Verify low two bits are clear.
1140 if ((CN->getZExtValue() & 3) == 0) {
1141 // If this address fits entirely in a 14-bit sext immediate field, codegen
1142 // this as "d, 0"
1143 short Imm;
1144 if (isIntS16Immediate(CN, Imm)) {
1145 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1146 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1147 CN->getValueType(0));
1148 return true;
1149 }
1150
1151 // Fold the low-part of 32-bit absolute addresses into addr mode.
1152 if (CN->getValueType(0) == MVT::i32 ||
1153 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1154 int Addr = (int)CN->getZExtValue();
1155
1156 // Otherwise, break this down into an LIS + disp.
1157 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1158 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1159 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1160 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1161 return true;
1162 }
1163 }
1164 }
1165
1166 Disp = DAG.getTargetConstant(0, getPointerTy());
1167 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1168 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1169 else
1170 Base = N;
1171 return true; // [r+0]
1172 }
1173
1174
1175 /// getPreIndexedAddressParts - returns true by value, base pointer and
1176 /// offset pointer and addressing mode by reference if the node's address
1177 /// can be legally represented as pre-indexed load / store address.
getPreIndexedAddressParts(SDNode * N,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const1178 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1179 SDValue &Offset,
1180 ISD::MemIndexedMode &AM,
1181 SelectionDAG &DAG) const {
1182 if (DisablePPCPreinc) return false;
1183
1184 SDValue Ptr;
1185 EVT VT;
1186 unsigned Alignment;
1187 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1188 Ptr = LD->getBasePtr();
1189 VT = LD->getMemoryVT();
1190 Alignment = LD->getAlignment();
1191 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1192 Ptr = ST->getBasePtr();
1193 VT = ST->getMemoryVT();
1194 Alignment = ST->getAlignment();
1195 } else
1196 return false;
1197
1198 // PowerPC doesn't have preinc load/store instructions for vectors.
1199 if (VT.isVector())
1200 return false;
1201
1202 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
1203 AM = ISD::PRE_INC;
1204 return true;
1205 }
1206
1207 // LDU/STU use reg+imm*4, others use reg+imm.
1208 if (VT != MVT::i64) {
1209 // reg + imm
1210 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1211 return false;
1212 } else {
1213 // LDU/STU need an address with at least 4-byte alignment.
1214 if (Alignment < 4)
1215 return false;
1216
1217 // reg + imm * 4.
1218 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1219 return false;
1220 }
1221
1222 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1223 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1224 // sext i32 to i64 when addr mode is r+i.
1225 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1226 LD->getExtensionType() == ISD::SEXTLOAD &&
1227 isa<ConstantSDNode>(Offset))
1228 return false;
1229 }
1230
1231 AM = ISD::PRE_INC;
1232 return true;
1233 }
1234
1235 //===----------------------------------------------------------------------===//
1236 // LowerOperation implementation
1237 //===----------------------------------------------------------------------===//
1238
1239 /// GetLabelAccessInfo - Return true if we should reference labels using a
1240 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
GetLabelAccessInfo(const TargetMachine & TM,unsigned & HiOpFlags,unsigned & LoOpFlags,const GlobalValue * GV=0)1241 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1242 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1243 HiOpFlags = PPCII::MO_HA16;
1244 LoOpFlags = PPCII::MO_LO16;
1245
1246 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1247 // non-darwin platform. We don't support PIC on other platforms yet.
1248 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1249 TM.getSubtarget<PPCSubtarget>().isDarwin();
1250 if (isPIC) {
1251 HiOpFlags |= PPCII::MO_PIC_FLAG;
1252 LoOpFlags |= PPCII::MO_PIC_FLAG;
1253 }
1254
1255 // If this is a reference to a global value that requires a non-lazy-ptr, make
1256 // sure that instruction lowering adds it.
1257 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1258 HiOpFlags |= PPCII::MO_NLP_FLAG;
1259 LoOpFlags |= PPCII::MO_NLP_FLAG;
1260
1261 if (GV->hasHiddenVisibility()) {
1262 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1263 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1264 }
1265 }
1266
1267 return isPIC;
1268 }
1269
LowerLabelRef(SDValue HiPart,SDValue LoPart,bool isPIC,SelectionDAG & DAG)1270 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1271 SelectionDAG &DAG) {
1272 EVT PtrVT = HiPart.getValueType();
1273 SDValue Zero = DAG.getConstant(0, PtrVT);
1274 DebugLoc DL = HiPart.getDebugLoc();
1275
1276 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1277 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1278
1279 // With PIC, the first instruction is actually "GR+hi(&G)".
1280 if (isPIC)
1281 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1282 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1283
1284 // Generate non-pic code that has direct accesses to the constant pool.
1285 // The address of the global is just (hi(&g)+lo(&g)).
1286 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1287 }
1288
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const1289 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1290 SelectionDAG &DAG) const {
1291 EVT PtrVT = Op.getValueType();
1292 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1293 const Constant *C = CP->getConstVal();
1294
1295 // 64-bit SVR4 ABI code is always position-independent.
1296 // The actual address of the GlobalValue is stored in the TOC.
1297 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1298 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1299 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1300 DAG.getRegister(PPC::X2, MVT::i64));
1301 }
1302
1303 unsigned MOHiFlag, MOLoFlag;
1304 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1305 SDValue CPIHi =
1306 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1307 SDValue CPILo =
1308 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1309 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1310 }
1311
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1312 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1313 EVT PtrVT = Op.getValueType();
1314 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1315
1316 // 64-bit SVR4 ABI code is always position-independent.
1317 // The actual address of the GlobalValue is stored in the TOC.
1318 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1319 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1320 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1321 DAG.getRegister(PPC::X2, MVT::i64));
1322 }
1323
1324 unsigned MOHiFlag, MOLoFlag;
1325 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1326 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1327 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1328 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1329 }
1330
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1331 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1332 SelectionDAG &DAG) const {
1333 EVT PtrVT = Op.getValueType();
1334
1335 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1336
1337 unsigned MOHiFlag, MOLoFlag;
1338 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1339 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1340 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1341 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1342 }
1343
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1344 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1345 SelectionDAG &DAG) const {
1346
1347 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1348 DebugLoc dl = GA->getDebugLoc();
1349 const GlobalValue *GV = GA->getGlobal();
1350 EVT PtrVT = getPointerTy();
1351 bool is64bit = PPCSubTarget.isPPC64();
1352
1353 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1354
1355 if (Model == TLSModel::LocalExec) {
1356 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1357 PPCII::MO_TPREL16_HA);
1358 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1359 PPCII::MO_TPREL16_LO);
1360 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1361 is64bit ? MVT::i64 : MVT::i32);
1362 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1363 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1364 }
1365
1366 if (!is64bit)
1367 llvm_unreachable("only local-exec is currently supported for ppc32");
1368
1369 if (Model == TLSModel::InitialExec) {
1370 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1371 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1372 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1373 PtrVT, GOTReg, TGA);
1374 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1375 PtrVT, TGA, TPOffsetHi);
1376 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1377 }
1378
1379 if (Model == TLSModel::GeneralDynamic) {
1380 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1381 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1382 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1383 GOTReg, TGA);
1384 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1385 GOTEntryHi, TGA);
1386
1387 // We need a chain node, and don't have one handy. The underlying
1388 // call has no side effects, so using the function entry node
1389 // suffices.
1390 SDValue Chain = DAG.getEntryNode();
1391 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1392 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1393 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1394 PtrVT, ParmReg, TGA);
1395 // The return value from GET_TLS_ADDR really is in X3 already, but
1396 // some hacks are needed here to tie everything together. The extra
1397 // copies dissolve during subsequent transforms.
1398 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1399 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1400 }
1401
1402 if (Model == TLSModel::LocalDynamic) {
1403 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1404 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1405 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1406 GOTReg, TGA);
1407 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1408 GOTEntryHi, TGA);
1409
1410 // We need a chain node, and don't have one handy. The underlying
1411 // call has no side effects, so using the function entry node
1412 // suffices.
1413 SDValue Chain = DAG.getEntryNode();
1414 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1415 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1416 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1417 PtrVT, ParmReg, TGA);
1418 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1419 // some hacks are needed here to tie everything together. The extra
1420 // copies dissolve during subsequent transforms.
1421 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1422 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1423 Chain, ParmReg, TGA);
1424 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1425 }
1426
1427 llvm_unreachable("Unknown TLS model!");
1428 }
1429
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1430 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1431 SelectionDAG &DAG) const {
1432 EVT PtrVT = Op.getValueType();
1433 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1434 DebugLoc DL = GSDN->getDebugLoc();
1435 const GlobalValue *GV = GSDN->getGlobal();
1436
1437 // 64-bit SVR4 ABI code is always position-independent.
1438 // The actual address of the GlobalValue is stored in the TOC.
1439 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1440 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1441 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1442 DAG.getRegister(PPC::X2, MVT::i64));
1443 }
1444
1445 unsigned MOHiFlag, MOLoFlag;
1446 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1447
1448 SDValue GAHi =
1449 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1450 SDValue GALo =
1451 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1452
1453 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1454
1455 // If the global reference is actually to a non-lazy-pointer, we have to do an
1456 // extra load to get the address of the global.
1457 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1458 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1459 false, false, false, 0);
1460 return Ptr;
1461 }
1462
LowerSETCC(SDValue Op,SelectionDAG & DAG) const1463 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1464 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1465 DebugLoc dl = Op.getDebugLoc();
1466
1467 // If we're comparing for equality to zero, expose the fact that this is
1468 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1469 // fold the new nodes.
1470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1471 if (C->isNullValue() && CC == ISD::SETEQ) {
1472 EVT VT = Op.getOperand(0).getValueType();
1473 SDValue Zext = Op.getOperand(0);
1474 if (VT.bitsLT(MVT::i32)) {
1475 VT = MVT::i32;
1476 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1477 }
1478 unsigned Log2b = Log2_32(VT.getSizeInBits());
1479 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1480 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1481 DAG.getConstant(Log2b, MVT::i32));
1482 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1483 }
1484 // Leave comparisons against 0 and -1 alone for now, since they're usually
1485 // optimized. FIXME: revisit this when we can custom lower all setcc
1486 // optimizations.
1487 if (C->isAllOnesValue() || C->isNullValue())
1488 return SDValue();
1489 }
1490
1491 // If we have an integer seteq/setne, turn it into a compare against zero
1492 // by xor'ing the rhs with the lhs, which is faster than setting a
1493 // condition register, reading it back out, and masking the correct bit. The
1494 // normal approach here uses sub to do this instead of xor. Using xor exposes
1495 // the result to other bit-twiddling opportunities.
1496 EVT LHSVT = Op.getOperand(0).getValueType();
1497 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1498 EVT VT = Op.getValueType();
1499 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1500 Op.getOperand(1));
1501 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1502 }
1503 return SDValue();
1504 }
1505
LowerVAARG(SDValue Op,SelectionDAG & DAG,const PPCSubtarget & Subtarget) const1506 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1507 const PPCSubtarget &Subtarget) const {
1508 SDNode *Node = Op.getNode();
1509 EVT VT = Node->getValueType(0);
1510 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1511 SDValue InChain = Node->getOperand(0);
1512 SDValue VAListPtr = Node->getOperand(1);
1513 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1514 DebugLoc dl = Node->getDebugLoc();
1515
1516 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1517
1518 // gpr_index
1519 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1520 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1521 false, false, 0);
1522 InChain = GprIndex.getValue(1);
1523
1524 if (VT == MVT::i64) {
1525 // Check if GprIndex is even
1526 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1527 DAG.getConstant(1, MVT::i32));
1528 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1529 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1530 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1531 DAG.getConstant(1, MVT::i32));
1532 // Align GprIndex to be even if it isn't
1533 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1534 GprIndex);
1535 }
1536
1537 // fpr index is 1 byte after gpr
1538 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1539 DAG.getConstant(1, MVT::i32));
1540
1541 // fpr
1542 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1543 FprPtr, MachinePointerInfo(SV), MVT::i8,
1544 false, false, 0);
1545 InChain = FprIndex.getValue(1);
1546
1547 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1548 DAG.getConstant(8, MVT::i32));
1549
1550 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1551 DAG.getConstant(4, MVT::i32));
1552
1553 // areas
1554 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1555 MachinePointerInfo(), false, false,
1556 false, 0);
1557 InChain = OverflowArea.getValue(1);
1558
1559 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1560 MachinePointerInfo(), false, false,
1561 false, 0);
1562 InChain = RegSaveArea.getValue(1);
1563
1564 // select overflow_area if index > 8
1565 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1566 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1567
1568 // adjustment constant gpr_index * 4/8
1569 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1570 VT.isInteger() ? GprIndex : FprIndex,
1571 DAG.getConstant(VT.isInteger() ? 4 : 8,
1572 MVT::i32));
1573
1574 // OurReg = RegSaveArea + RegConstant
1575 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1576 RegConstant);
1577
1578 // Floating types are 32 bytes into RegSaveArea
1579 if (VT.isFloatingPoint())
1580 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1581 DAG.getConstant(32, MVT::i32));
1582
1583 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1584 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1585 VT.isInteger() ? GprIndex : FprIndex,
1586 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1587 MVT::i32));
1588
1589 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1590 VT.isInteger() ? VAListPtr : FprPtr,
1591 MachinePointerInfo(SV),
1592 MVT::i8, false, false, 0);
1593
1594 // determine if we should load from reg_save_area or overflow_area
1595 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1596
1597 // increase overflow_area by 4/8 if gpr/fpr > 8
1598 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1599 DAG.getConstant(VT.isInteger() ? 4 : 8,
1600 MVT::i32));
1601
1602 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1603 OverflowAreaPlusN);
1604
1605 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1606 OverflowAreaPtr,
1607 MachinePointerInfo(),
1608 MVT::i32, false, false, 0);
1609
1610 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1611 false, false, false, 0);
1612 }
1613
LowerADJUST_TRAMPOLINE(SDValue Op,SelectionDAG & DAG) const1614 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1615 SelectionDAG &DAG) const {
1616 return Op.getOperand(0);
1617 }
1618
LowerINIT_TRAMPOLINE(SDValue Op,SelectionDAG & DAG) const1619 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1620 SelectionDAG &DAG) const {
1621 SDValue Chain = Op.getOperand(0);
1622 SDValue Trmp = Op.getOperand(1); // trampoline
1623 SDValue FPtr = Op.getOperand(2); // nested function
1624 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1625 DebugLoc dl = Op.getDebugLoc();
1626
1627 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1628 bool isPPC64 = (PtrVT == MVT::i64);
1629 Type *IntPtrTy =
1630 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1631 *DAG.getContext());
1632
1633 TargetLowering::ArgListTy Args;
1634 TargetLowering::ArgListEntry Entry;
1635
1636 Entry.Ty = IntPtrTy;
1637 Entry.Node = Trmp; Args.push_back(Entry);
1638
1639 // TrampSize == (isPPC64 ? 48 : 40);
1640 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1641 isPPC64 ? MVT::i64 : MVT::i32);
1642 Args.push_back(Entry);
1643
1644 Entry.Node = FPtr; Args.push_back(Entry);
1645 Entry.Node = Nest; Args.push_back(Entry);
1646
1647 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1648 TargetLowering::CallLoweringInfo CLI(Chain,
1649 Type::getVoidTy(*DAG.getContext()),
1650 false, false, false, false, 0,
1651 CallingConv::C,
1652 /*isTailCall=*/false,
1653 /*doesNotRet=*/false,
1654 /*isReturnValueUsed=*/true,
1655 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1656 Args, DAG, dl);
1657 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1658
1659 return CallResult.second;
1660 }
1661
LowerVASTART(SDValue Op,SelectionDAG & DAG,const PPCSubtarget & Subtarget) const1662 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1663 const PPCSubtarget &Subtarget) const {
1664 MachineFunction &MF = DAG.getMachineFunction();
1665 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1666
1667 DebugLoc dl = Op.getDebugLoc();
1668
1669 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1670 // vastart just stores the address of the VarArgsFrameIndex slot into the
1671 // memory location argument.
1672 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1673 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1674 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1675 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1676 MachinePointerInfo(SV),
1677 false, false, 0);
1678 }
1679
1680 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1681 // We suppose the given va_list is already allocated.
1682 //
1683 // typedef struct {
1684 // char gpr; /* index into the array of 8 GPRs
1685 // * stored in the register save area
1686 // * gpr=0 corresponds to r3,
1687 // * gpr=1 to r4, etc.
1688 // */
1689 // char fpr; /* index into the array of 8 FPRs
1690 // * stored in the register save area
1691 // * fpr=0 corresponds to f1,
1692 // * fpr=1 to f2, etc.
1693 // */
1694 // char *overflow_arg_area;
1695 // /* location on stack that holds
1696 // * the next overflow argument
1697 // */
1698 // char *reg_save_area;
1699 // /* where r3:r10 and f1:f8 (if saved)
1700 // * are stored
1701 // */
1702 // } va_list[1];
1703
1704
1705 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1706 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1707
1708
1709 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1710
1711 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1712 PtrVT);
1713 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1714 PtrVT);
1715
1716 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1717 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1718
1719 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1720 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1721
1722 uint64_t FPROffset = 1;
1723 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1724
1725 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1726
1727 // Store first byte : number of int regs
1728 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1729 Op.getOperand(1),
1730 MachinePointerInfo(SV),
1731 MVT::i8, false, false, 0);
1732 uint64_t nextOffset = FPROffset;
1733 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1734 ConstFPROffset);
1735
1736 // Store second byte : number of float regs
1737 SDValue secondStore =
1738 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1739 MachinePointerInfo(SV, nextOffset), MVT::i8,
1740 false, false, 0);
1741 nextOffset += StackOffset;
1742 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1743
1744 // Store second word : arguments given on stack
1745 SDValue thirdStore =
1746 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1747 MachinePointerInfo(SV, nextOffset),
1748 false, false, 0);
1749 nextOffset += FrameOffset;
1750 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1751
1752 // Store third word : arguments given in registers
1753 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1754 MachinePointerInfo(SV, nextOffset),
1755 false, false, 0);
1756
1757 }
1758
1759 #include "PPCGenCallingConv.inc"
1760
CC_PPC32_SVR4_Custom_Dummy(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)1761 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1762 CCValAssign::LocInfo &LocInfo,
1763 ISD::ArgFlagsTy &ArgFlags,
1764 CCState &State) {
1765 return true;
1766 }
1767
CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)1768 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1769 MVT &LocVT,
1770 CCValAssign::LocInfo &LocInfo,
1771 ISD::ArgFlagsTy &ArgFlags,
1772 CCState &State) {
1773 static const uint16_t ArgRegs[] = {
1774 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1775 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1776 };
1777 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1778
1779 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1780
1781 // Skip one register if the first unallocated register has an even register
1782 // number and there are still argument registers available which have not been
1783 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1784 // need to skip a register if RegNum is odd.
1785 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1786 State.AllocateReg(ArgRegs[RegNum]);
1787 }
1788
1789 // Always return false here, as this function only makes sure that the first
1790 // unallocated register has an odd register number and does not actually
1791 // allocate a register for the current argument.
1792 return false;
1793 }
1794
CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)1795 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1796 MVT &LocVT,
1797 CCValAssign::LocInfo &LocInfo,
1798 ISD::ArgFlagsTy &ArgFlags,
1799 CCState &State) {
1800 static const uint16_t ArgRegs[] = {
1801 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1802 PPC::F8
1803 };
1804
1805 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1806
1807 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1808
1809 // If there is only one Floating-point register left we need to put both f64
1810 // values of a split ppc_fp128 value on the stack.
1811 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1812 State.AllocateReg(ArgRegs[RegNum]);
1813 }
1814
1815 // Always return false here, as this function only makes sure that the two f64
1816 // values a ppc_fp128 value is split into are both passed in registers or both
1817 // passed on the stack and does not actually allocate a register for the
1818 // current argument.
1819 return false;
1820 }
1821
1822 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1823 /// on Darwin.
GetFPR()1824 static const uint16_t *GetFPR() {
1825 static const uint16_t FPR[] = {
1826 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1827 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1828 };
1829
1830 return FPR;
1831 }
1832
1833 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1834 /// the stack.
CalculateStackSlotSize(EVT ArgVT,ISD::ArgFlagsTy Flags,unsigned PtrByteSize)1835 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1836 unsigned PtrByteSize) {
1837 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1838 if (Flags.isByVal())
1839 ArgSize = Flags.getByValSize();
1840 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1841
1842 return ArgSize;
1843 }
1844
1845 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1846 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1847 CallingConv::ID CallConv, bool isVarArg,
1848 const SmallVectorImpl<ISD::InputArg>
1849 &Ins,
1850 DebugLoc dl, SelectionDAG &DAG,
1851 SmallVectorImpl<SDValue> &InVals)
1852 const {
1853 if (PPCSubTarget.isSVR4ABI()) {
1854 if (PPCSubTarget.isPPC64())
1855 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1856 dl, DAG, InVals);
1857 else
1858 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1859 dl, DAG, InVals);
1860 } else {
1861 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1862 dl, DAG, InVals);
1863 }
1864 }
1865
1866 SDValue
LowerFormalArguments_32SVR4(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1867 PPCTargetLowering::LowerFormalArguments_32SVR4(
1868 SDValue Chain,
1869 CallingConv::ID CallConv, bool isVarArg,
1870 const SmallVectorImpl<ISD::InputArg>
1871 &Ins,
1872 DebugLoc dl, SelectionDAG &DAG,
1873 SmallVectorImpl<SDValue> &InVals) const {
1874
1875 // 32-bit SVR4 ABI Stack Frame Layout:
1876 // +-----------------------------------+
1877 // +--> | Back chain |
1878 // | +-----------------------------------+
1879 // | | Floating-point register save area |
1880 // | +-----------------------------------+
1881 // | | General register save area |
1882 // | +-----------------------------------+
1883 // | | CR save word |
1884 // | +-----------------------------------+
1885 // | | VRSAVE save word |
1886 // | +-----------------------------------+
1887 // | | Alignment padding |
1888 // | +-----------------------------------+
1889 // | | Vector register save area |
1890 // | +-----------------------------------+
1891 // | | Local variable space |
1892 // | +-----------------------------------+
1893 // | | Parameter list area |
1894 // | +-----------------------------------+
1895 // | | LR save word |
1896 // | +-----------------------------------+
1897 // SP--> +--- | Back chain |
1898 // +-----------------------------------+
1899 //
1900 // Specifications:
1901 // System V Application Binary Interface PowerPC Processor Supplement
1902 // AltiVec Technology Programming Interface Manual
1903
1904 MachineFunction &MF = DAG.getMachineFunction();
1905 MachineFrameInfo *MFI = MF.getFrameInfo();
1906 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1907
1908 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1909 // Potential tail calls could cause overwriting of argument stack slots.
1910 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1911 (CallConv == CallingConv::Fast));
1912 unsigned PtrByteSize = 4;
1913
1914 // Assign locations to all of the incoming arguments.
1915 SmallVector<CCValAssign, 16> ArgLocs;
1916 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1917 getTargetMachine(), ArgLocs, *DAG.getContext());
1918
1919 // Reserve space for the linkage area on the stack.
1920 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1921
1922 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1923
1924 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1925 CCValAssign &VA = ArgLocs[i];
1926
1927 // Arguments stored in registers.
1928 if (VA.isRegLoc()) {
1929 const TargetRegisterClass *RC;
1930 EVT ValVT = VA.getValVT();
1931
1932 switch (ValVT.getSimpleVT().SimpleTy) {
1933 default:
1934 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1935 case MVT::i32:
1936 RC = &PPC::GPRCRegClass;
1937 break;
1938 case MVT::f32:
1939 RC = &PPC::F4RCRegClass;
1940 break;
1941 case MVT::f64:
1942 RC = &PPC::F8RCRegClass;
1943 break;
1944 case MVT::v16i8:
1945 case MVT::v8i16:
1946 case MVT::v4i32:
1947 case MVT::v4f32:
1948 RC = &PPC::VRRCRegClass;
1949 break;
1950 }
1951
1952 // Transform the arguments stored in physical registers into virtual ones.
1953 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1954 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1955
1956 InVals.push_back(ArgValue);
1957 } else {
1958 // Argument stored in memory.
1959 assert(VA.isMemLoc());
1960
1961 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1962 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1963 isImmutable);
1964
1965 // Create load nodes to retrieve arguments from the stack.
1966 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1967 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1968 MachinePointerInfo(),
1969 false, false, false, 0));
1970 }
1971 }
1972
1973 // Assign locations to all of the incoming aggregate by value arguments.
1974 // Aggregates passed by value are stored in the local variable space of the
1975 // caller's stack frame, right above the parameter list area.
1976 SmallVector<CCValAssign, 16> ByValArgLocs;
1977 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1978 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1979
1980 // Reserve stack space for the allocations in CCInfo.
1981 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1982
1983 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
1984
1985 // Area that is at least reserved in the caller of this function.
1986 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1987
1988 // Set the size that is at least reserved in caller of this function. Tail
1989 // call optimized function's reserved stack space needs to be aligned so that
1990 // taking the difference between two stack areas will result in an aligned
1991 // stack.
1992 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1993
1994 MinReservedArea =
1995 std::max(MinReservedArea,
1996 PPCFrameLowering::getMinCallFrameSize(false, false));
1997
1998 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1999 getStackAlignment();
2000 unsigned AlignMask = TargetAlign-1;
2001 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2002
2003 FI->setMinReservedArea(MinReservedArea);
2004
2005 SmallVector<SDValue, 8> MemOps;
2006
2007 // If the function takes variable number of arguments, make a frame index for
2008 // the start of the first vararg value... for expansion of llvm.va_start.
2009 if (isVarArg) {
2010 static const uint16_t GPArgRegs[] = {
2011 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2012 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2013 };
2014 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2015
2016 static const uint16_t FPArgRegs[] = {
2017 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2018 PPC::F8
2019 };
2020 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2021
2022 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2023 NumGPArgRegs));
2024 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2025 NumFPArgRegs));
2026
2027 // Make room for NumGPArgRegs and NumFPArgRegs.
2028 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2029 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2030
2031 FuncInfo->setVarArgsStackOffset(
2032 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2033 CCInfo.getNextStackOffset(), true));
2034
2035 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2036 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2037
2038 // The fixed integer arguments of a variadic function are stored to the
2039 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2040 // the result of va_next.
2041 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2042 // Get an existing live-in vreg, or add a new one.
2043 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2044 if (!VReg)
2045 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2046
2047 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2048 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2049 MachinePointerInfo(), false, false, 0);
2050 MemOps.push_back(Store);
2051 // Increment the address by four for the next argument to store
2052 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2053 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2054 }
2055
2056 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2057 // is set.
2058 // The double arguments are stored to the VarArgsFrameIndex
2059 // on the stack.
2060 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2061 // Get an existing live-in vreg, or add a new one.
2062 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2063 if (!VReg)
2064 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2065
2066 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2067 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2068 MachinePointerInfo(), false, false, 0);
2069 MemOps.push_back(Store);
2070 // Increment the address by eight for the next argument to store
2071 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2072 PtrVT);
2073 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2074 }
2075 }
2076
2077 if (!MemOps.empty())
2078 Chain = DAG.getNode(ISD::TokenFactor, dl,
2079 MVT::Other, &MemOps[0], MemOps.size());
2080
2081 return Chain;
2082 }
2083
2084 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2085 // value to MVT::i64 and then truncate to the correct register size.
2086 SDValue
extendArgForPPC64(ISD::ArgFlagsTy Flags,EVT ObjectVT,SelectionDAG & DAG,SDValue ArgVal,DebugLoc dl) const2087 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2088 SelectionDAG &DAG, SDValue ArgVal,
2089 DebugLoc dl) const {
2090 if (Flags.isSExt())
2091 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2092 DAG.getValueType(ObjectVT));
2093 else if (Flags.isZExt())
2094 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2095 DAG.getValueType(ObjectVT));
2096
2097 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2098 }
2099
2100 // Set the size that is at least reserved in caller of this function. Tail
2101 // call optimized functions' reserved stack space needs to be aligned so that
2102 // taking the difference between two stack areas will result in an aligned
2103 // stack.
2104 void
setMinReservedArea(MachineFunction & MF,SelectionDAG & DAG,unsigned nAltivecParamsAtEnd,unsigned MinReservedArea,bool isPPC64) const2105 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2106 unsigned nAltivecParamsAtEnd,
2107 unsigned MinReservedArea,
2108 bool isPPC64) const {
2109 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2110 // Add the Altivec parameters at the end, if needed.
2111 if (nAltivecParamsAtEnd) {
2112 MinReservedArea = ((MinReservedArea+15)/16)*16;
2113 MinReservedArea += 16*nAltivecParamsAtEnd;
2114 }
2115 MinReservedArea =
2116 std::max(MinReservedArea,
2117 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2118 unsigned TargetAlign
2119 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2120 getStackAlignment();
2121 unsigned AlignMask = TargetAlign-1;
2122 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2123 FI->setMinReservedArea(MinReservedArea);
2124 }
2125
2126 SDValue
LowerFormalArguments_64SVR4(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2127 PPCTargetLowering::LowerFormalArguments_64SVR4(
2128 SDValue Chain,
2129 CallingConv::ID CallConv, bool isVarArg,
2130 const SmallVectorImpl<ISD::InputArg>
2131 &Ins,
2132 DebugLoc dl, SelectionDAG &DAG,
2133 SmallVectorImpl<SDValue> &InVals) const {
2134 // TODO: add description of PPC stack frame format, or at least some docs.
2135 //
2136 MachineFunction &MF = DAG.getMachineFunction();
2137 MachineFrameInfo *MFI = MF.getFrameInfo();
2138 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2139
2140 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2141 // Potential tail calls could cause overwriting of argument stack slots.
2142 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2143 (CallConv == CallingConv::Fast));
2144 unsigned PtrByteSize = 8;
2145
2146 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2147 // Area that is at least reserved in caller of this function.
2148 unsigned MinReservedArea = ArgOffset;
2149
2150 static const uint16_t GPR[] = {
2151 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2152 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2153 };
2154
2155 static const uint16_t *FPR = GetFPR();
2156
2157 static const uint16_t VR[] = {
2158 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2159 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2160 };
2161
2162 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2163 const unsigned Num_FPR_Regs = 13;
2164 const unsigned Num_VR_Regs = array_lengthof(VR);
2165
2166 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2167
2168 // Add DAG nodes to load the arguments or copy them out of registers. On
2169 // entry to a function on PPC, the arguments start after the linkage area,
2170 // although the first ones are often in registers.
2171
2172 SmallVector<SDValue, 8> MemOps;
2173 unsigned nAltivecParamsAtEnd = 0;
2174 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2175 unsigned CurArgIdx = 0;
2176 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2177 SDValue ArgVal;
2178 bool needsLoad = false;
2179 EVT ObjectVT = Ins[ArgNo].VT;
2180 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2181 unsigned ArgSize = ObjSize;
2182 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2183 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2184 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2185
2186 unsigned CurArgOffset = ArgOffset;
2187
2188 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2189 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2190 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2191 if (isVarArg) {
2192 MinReservedArea = ((MinReservedArea+15)/16)*16;
2193 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2194 Flags,
2195 PtrByteSize);
2196 } else
2197 nAltivecParamsAtEnd++;
2198 } else
2199 // Calculate min reserved area.
2200 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2201 Flags,
2202 PtrByteSize);
2203
2204 // FIXME the codegen can be much improved in some cases.
2205 // We do not have to keep everything in memory.
2206 if (Flags.isByVal()) {
2207 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2208 ObjSize = Flags.getByValSize();
2209 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2210 // Empty aggregate parameters do not take up registers. Examples:
2211 // struct { } a;
2212 // union { } b;
2213 // int c[0];
2214 // etc. However, we have to provide a place-holder in InVals, so
2215 // pretend we have an 8-byte item at the current address for that
2216 // purpose.
2217 if (!ObjSize) {
2218 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2219 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2220 InVals.push_back(FIN);
2221 continue;
2222 }
2223 // All aggregates smaller than 8 bytes must be passed right-justified.
2224 if (ObjSize < PtrByteSize)
2225 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2226 // The value of the object is its address.
2227 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2228 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2229 InVals.push_back(FIN);
2230
2231 if (ObjSize < 8) {
2232 if (GPR_idx != Num_GPR_Regs) {
2233 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2234 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2235 SDValue Store;
2236
2237 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2238 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2239 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2240 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2241 MachinePointerInfo(FuncArg, CurArgOffset),
2242 ObjType, false, false, 0);
2243 } else {
2244 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2245 // store the whole register as-is to the parameter save area
2246 // slot. The address of the parameter was already calculated
2247 // above (InVals.push_back(FIN)) to be the right-justified
2248 // offset within the slot. For this store, we need a new
2249 // frame index that points at the beginning of the slot.
2250 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2251 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2252 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2253 MachinePointerInfo(FuncArg, ArgOffset),
2254 false, false, 0);
2255 }
2256
2257 MemOps.push_back(Store);
2258 ++GPR_idx;
2259 }
2260 // Whether we copied from a register or not, advance the offset
2261 // into the parameter save area by a full doubleword.
2262 ArgOffset += PtrByteSize;
2263 continue;
2264 }
2265
2266 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2267 // Store whatever pieces of the object are in registers
2268 // to memory. ArgOffset will be the address of the beginning
2269 // of the object.
2270 if (GPR_idx != Num_GPR_Regs) {
2271 unsigned VReg;
2272 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2273 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2274 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2275 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2276 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2277 MachinePointerInfo(FuncArg, ArgOffset),
2278 false, false, 0);
2279 MemOps.push_back(Store);
2280 ++GPR_idx;
2281 ArgOffset += PtrByteSize;
2282 } else {
2283 ArgOffset += ArgSize - j;
2284 break;
2285 }
2286 }
2287 continue;
2288 }
2289
2290 switch (ObjectVT.getSimpleVT().SimpleTy) {
2291 default: llvm_unreachable("Unhandled argument type!");
2292 case MVT::i32:
2293 case MVT::i64:
2294 if (GPR_idx != Num_GPR_Regs) {
2295 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2296 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2297
2298 if (ObjectVT == MVT::i32)
2299 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2300 // value to MVT::i64 and then truncate to the correct register size.
2301 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2302
2303 ++GPR_idx;
2304 } else {
2305 needsLoad = true;
2306 ArgSize = PtrByteSize;
2307 }
2308 ArgOffset += 8;
2309 break;
2310
2311 case MVT::f32:
2312 case MVT::f64:
2313 // Every 8 bytes of argument space consumes one of the GPRs available for
2314 // argument passing.
2315 if (GPR_idx != Num_GPR_Regs) {
2316 ++GPR_idx;
2317 }
2318 if (FPR_idx != Num_FPR_Regs) {
2319 unsigned VReg;
2320
2321 if (ObjectVT == MVT::f32)
2322 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2323 else
2324 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2325
2326 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2327 ++FPR_idx;
2328 } else {
2329 needsLoad = true;
2330 ArgSize = PtrByteSize;
2331 }
2332
2333 ArgOffset += 8;
2334 break;
2335 case MVT::v4f32:
2336 case MVT::v4i32:
2337 case MVT::v8i16:
2338 case MVT::v16i8:
2339 // Note that vector arguments in registers don't reserve stack space,
2340 // except in varargs functions.
2341 if (VR_idx != Num_VR_Regs) {
2342 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2343 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2344 if (isVarArg) {
2345 while ((ArgOffset % 16) != 0) {
2346 ArgOffset += PtrByteSize;
2347 if (GPR_idx != Num_GPR_Regs)
2348 GPR_idx++;
2349 }
2350 ArgOffset += 16;
2351 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2352 }
2353 ++VR_idx;
2354 } else {
2355 // Vectors are aligned.
2356 ArgOffset = ((ArgOffset+15)/16)*16;
2357 CurArgOffset = ArgOffset;
2358 ArgOffset += 16;
2359 needsLoad = true;
2360 }
2361 break;
2362 }
2363
2364 // We need to load the argument to a virtual register if we determined
2365 // above that we ran out of physical registers of the appropriate type.
2366 if (needsLoad) {
2367 int FI = MFI->CreateFixedObject(ObjSize,
2368 CurArgOffset + (ArgSize - ObjSize),
2369 isImmutable);
2370 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2371 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2372 false, false, false, 0);
2373 }
2374
2375 InVals.push_back(ArgVal);
2376 }
2377
2378 // Set the size that is at least reserved in caller of this function. Tail
2379 // call optimized functions' reserved stack space needs to be aligned so that
2380 // taking the difference between two stack areas will result in an aligned
2381 // stack.
2382 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2383
2384 // If the function takes variable number of arguments, make a frame index for
2385 // the start of the first vararg value... for expansion of llvm.va_start.
2386 if (isVarArg) {
2387 int Depth = ArgOffset;
2388
2389 FuncInfo->setVarArgsFrameIndex(
2390 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2391 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2392
2393 // If this function is vararg, store any remaining integer argument regs
2394 // to their spots on the stack so that they may be loaded by deferencing the
2395 // result of va_next.
2396 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2397 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2398 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2399 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2400 MachinePointerInfo(), false, false, 0);
2401 MemOps.push_back(Store);
2402 // Increment the address by four for the next argument to store
2403 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2404 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2405 }
2406 }
2407
2408 if (!MemOps.empty())
2409 Chain = DAG.getNode(ISD::TokenFactor, dl,
2410 MVT::Other, &MemOps[0], MemOps.size());
2411
2412 return Chain;
2413 }
2414
2415 SDValue
LowerFormalArguments_Darwin(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2416 PPCTargetLowering::LowerFormalArguments_Darwin(
2417 SDValue Chain,
2418 CallingConv::ID CallConv, bool isVarArg,
2419 const SmallVectorImpl<ISD::InputArg>
2420 &Ins,
2421 DebugLoc dl, SelectionDAG &DAG,
2422 SmallVectorImpl<SDValue> &InVals) const {
2423 // TODO: add description of PPC stack frame format, or at least some docs.
2424 //
2425 MachineFunction &MF = DAG.getMachineFunction();
2426 MachineFrameInfo *MFI = MF.getFrameInfo();
2427 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2428
2429 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2430 bool isPPC64 = PtrVT == MVT::i64;
2431 // Potential tail calls could cause overwriting of argument stack slots.
2432 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2433 (CallConv == CallingConv::Fast));
2434 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2435
2436 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2437 // Area that is at least reserved in caller of this function.
2438 unsigned MinReservedArea = ArgOffset;
2439
2440 static const uint16_t GPR_32[] = { // 32-bit registers.
2441 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2442 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2443 };
2444 static const uint16_t GPR_64[] = { // 64-bit registers.
2445 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2446 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2447 };
2448
2449 static const uint16_t *FPR = GetFPR();
2450
2451 static const uint16_t VR[] = {
2452 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2453 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2454 };
2455
2456 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2457 const unsigned Num_FPR_Regs = 13;
2458 const unsigned Num_VR_Regs = array_lengthof( VR);
2459
2460 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2461
2462 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2463
2464 // In 32-bit non-varargs functions, the stack space for vectors is after the
2465 // stack space for non-vectors. We do not use this space unless we have
2466 // too many vectors to fit in registers, something that only occurs in
2467 // constructed examples:), but we have to walk the arglist to figure
2468 // that out...for the pathological case, compute VecArgOffset as the
2469 // start of the vector parameter area. Computing VecArgOffset is the
2470 // entire point of the following loop.
2471 unsigned VecArgOffset = ArgOffset;
2472 if (!isVarArg && !isPPC64) {
2473 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2474 ++ArgNo) {
2475 EVT ObjectVT = Ins[ArgNo].VT;
2476 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2477
2478 if (Flags.isByVal()) {
2479 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2480 unsigned ObjSize = Flags.getByValSize();
2481 unsigned ArgSize =
2482 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2483 VecArgOffset += ArgSize;
2484 continue;
2485 }
2486
2487 switch(ObjectVT.getSimpleVT().SimpleTy) {
2488 default: llvm_unreachable("Unhandled argument type!");
2489 case MVT::i32:
2490 case MVT::f32:
2491 VecArgOffset += 4;
2492 break;
2493 case MVT::i64: // PPC64
2494 case MVT::f64:
2495 // FIXME: We are guaranteed to be !isPPC64 at this point.
2496 // Does MVT::i64 apply?
2497 VecArgOffset += 8;
2498 break;
2499 case MVT::v4f32:
2500 case MVT::v4i32:
2501 case MVT::v8i16:
2502 case MVT::v16i8:
2503 // Nothing to do, we're only looking at Nonvector args here.
2504 break;
2505 }
2506 }
2507 }
2508 // We've found where the vector parameter area in memory is. Skip the
2509 // first 12 parameters; these don't use that memory.
2510 VecArgOffset = ((VecArgOffset+15)/16)*16;
2511 VecArgOffset += 12*16;
2512
2513 // Add DAG nodes to load the arguments or copy them out of registers. On
2514 // entry to a function on PPC, the arguments start after the linkage area,
2515 // although the first ones are often in registers.
2516
2517 SmallVector<SDValue, 8> MemOps;
2518 unsigned nAltivecParamsAtEnd = 0;
2519 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2520 // When passing anonymous aggregates, this is currently not true.
2521 // See LowerFormalArguments_64SVR4 for a fix.
2522 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2523 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2524 SDValue ArgVal;
2525 bool needsLoad = false;
2526 EVT ObjectVT = Ins[ArgNo].VT;
2527 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2528 unsigned ArgSize = ObjSize;
2529 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2530
2531 unsigned CurArgOffset = ArgOffset;
2532
2533 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2534 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2535 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2536 if (isVarArg || isPPC64) {
2537 MinReservedArea = ((MinReservedArea+15)/16)*16;
2538 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2539 Flags,
2540 PtrByteSize);
2541 } else nAltivecParamsAtEnd++;
2542 } else
2543 // Calculate min reserved area.
2544 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2545 Flags,
2546 PtrByteSize);
2547
2548 // FIXME the codegen can be much improved in some cases.
2549 // We do not have to keep everything in memory.
2550 if (Flags.isByVal()) {
2551 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2552 ObjSize = Flags.getByValSize();
2553 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2554 // Objects of size 1 and 2 are right justified, everything else is
2555 // left justified. This means the memory address is adjusted forwards.
2556 if (ObjSize==1 || ObjSize==2) {
2557 CurArgOffset = CurArgOffset + (4 - ObjSize);
2558 }
2559 // The value of the object is its address.
2560 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2561 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2562 InVals.push_back(FIN);
2563 if (ObjSize==1 || ObjSize==2) {
2564 if (GPR_idx != Num_GPR_Regs) {
2565 unsigned VReg;
2566 if (isPPC64)
2567 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2568 else
2569 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2570 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2571 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2572 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2573 MachinePointerInfo(FuncArg,
2574 CurArgOffset),
2575 ObjType, false, false, 0);
2576 MemOps.push_back(Store);
2577 ++GPR_idx;
2578 }
2579
2580 ArgOffset += PtrByteSize;
2581
2582 continue;
2583 }
2584 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2585 // Store whatever pieces of the object are in registers
2586 // to memory. ArgOffset will be the address of the beginning
2587 // of the object.
2588 if (GPR_idx != Num_GPR_Regs) {
2589 unsigned VReg;
2590 if (isPPC64)
2591 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2592 else
2593 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2594 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2595 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2596 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2597 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2598 MachinePointerInfo(FuncArg, ArgOffset),
2599 false, false, 0);
2600 MemOps.push_back(Store);
2601 ++GPR_idx;
2602 ArgOffset += PtrByteSize;
2603 } else {
2604 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2605 break;
2606 }
2607 }
2608 continue;
2609 }
2610
2611 switch (ObjectVT.getSimpleVT().SimpleTy) {
2612 default: llvm_unreachable("Unhandled argument type!");
2613 case MVT::i32:
2614 if (!isPPC64) {
2615 if (GPR_idx != Num_GPR_Regs) {
2616 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2617 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2618 ++GPR_idx;
2619 } else {
2620 needsLoad = true;
2621 ArgSize = PtrByteSize;
2622 }
2623 // All int arguments reserve stack space in the Darwin ABI.
2624 ArgOffset += PtrByteSize;
2625 break;
2626 }
2627 // FALLTHROUGH
2628 case MVT::i64: // PPC64
2629 if (GPR_idx != Num_GPR_Regs) {
2630 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2631 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2632
2633 if (ObjectVT == MVT::i32)
2634 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2635 // value to MVT::i64 and then truncate to the correct register size.
2636 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2637
2638 ++GPR_idx;
2639 } else {
2640 needsLoad = true;
2641 ArgSize = PtrByteSize;
2642 }
2643 // All int arguments reserve stack space in the Darwin ABI.
2644 ArgOffset += 8;
2645 break;
2646
2647 case MVT::f32:
2648 case MVT::f64:
2649 // Every 4 bytes of argument space consumes one of the GPRs available for
2650 // argument passing.
2651 if (GPR_idx != Num_GPR_Regs) {
2652 ++GPR_idx;
2653 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2654 ++GPR_idx;
2655 }
2656 if (FPR_idx != Num_FPR_Regs) {
2657 unsigned VReg;
2658
2659 if (ObjectVT == MVT::f32)
2660 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2661 else
2662 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2663
2664 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2665 ++FPR_idx;
2666 } else {
2667 needsLoad = true;
2668 }
2669
2670 // All FP arguments reserve stack space in the Darwin ABI.
2671 ArgOffset += isPPC64 ? 8 : ObjSize;
2672 break;
2673 case MVT::v4f32:
2674 case MVT::v4i32:
2675 case MVT::v8i16:
2676 case MVT::v16i8:
2677 // Note that vector arguments in registers don't reserve stack space,
2678 // except in varargs functions.
2679 if (VR_idx != Num_VR_Regs) {
2680 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2681 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2682 if (isVarArg) {
2683 while ((ArgOffset % 16) != 0) {
2684 ArgOffset += PtrByteSize;
2685 if (GPR_idx != Num_GPR_Regs)
2686 GPR_idx++;
2687 }
2688 ArgOffset += 16;
2689 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2690 }
2691 ++VR_idx;
2692 } else {
2693 if (!isVarArg && !isPPC64) {
2694 // Vectors go after all the nonvectors.
2695 CurArgOffset = VecArgOffset;
2696 VecArgOffset += 16;
2697 } else {
2698 // Vectors are aligned.
2699 ArgOffset = ((ArgOffset+15)/16)*16;
2700 CurArgOffset = ArgOffset;
2701 ArgOffset += 16;
2702 }
2703 needsLoad = true;
2704 }
2705 break;
2706 }
2707
2708 // We need to load the argument to a virtual register if we determined above
2709 // that we ran out of physical registers of the appropriate type.
2710 if (needsLoad) {
2711 int FI = MFI->CreateFixedObject(ObjSize,
2712 CurArgOffset + (ArgSize - ObjSize),
2713 isImmutable);
2714 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2715 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2716 false, false, false, 0);
2717 }
2718
2719 InVals.push_back(ArgVal);
2720 }
2721
2722 // Set the size that is at least reserved in caller of this function. Tail
2723 // call optimized functions' reserved stack space needs to be aligned so that
2724 // taking the difference between two stack areas will result in an aligned
2725 // stack.
2726 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2727
2728 // If the function takes variable number of arguments, make a frame index for
2729 // the start of the first vararg value... for expansion of llvm.va_start.
2730 if (isVarArg) {
2731 int Depth = ArgOffset;
2732
2733 FuncInfo->setVarArgsFrameIndex(
2734 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2735 Depth, true));
2736 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2737
2738 // If this function is vararg, store any remaining integer argument regs
2739 // to their spots on the stack so that they may be loaded by deferencing the
2740 // result of va_next.
2741 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2742 unsigned VReg;
2743
2744 if (isPPC64)
2745 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2746 else
2747 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2748
2749 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2750 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2751 MachinePointerInfo(), false, false, 0);
2752 MemOps.push_back(Store);
2753 // Increment the address by four for the next argument to store
2754 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2755 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2756 }
2757 }
2758
2759 if (!MemOps.empty())
2760 Chain = DAG.getNode(ISD::TokenFactor, dl,
2761 MVT::Other, &MemOps[0], MemOps.size());
2762
2763 return Chain;
2764 }
2765
2766 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2767 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2768 static unsigned
CalculateParameterAndLinkageAreaSize(SelectionDAG & DAG,bool isPPC64,bool isVarArg,unsigned CC,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,unsigned & nAltivecParamsAtEnd)2769 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2770 bool isPPC64,
2771 bool isVarArg,
2772 unsigned CC,
2773 const SmallVectorImpl<ISD::OutputArg>
2774 &Outs,
2775 const SmallVectorImpl<SDValue> &OutVals,
2776 unsigned &nAltivecParamsAtEnd) {
2777 // Count how many bytes are to be pushed on the stack, including the linkage
2778 // area, and parameter passing area. We start with 24/48 bytes, which is
2779 // prereserved space for [SP][CR][LR][3 x unused].
2780 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2781 unsigned NumOps = Outs.size();
2782 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2783
2784 // Add up all the space actually used.
2785 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2786 // they all go in registers, but we must reserve stack space for them for
2787 // possible use by the caller. In varargs or 64-bit calls, parameters are
2788 // assigned stack space in order, with padding so Altivec parameters are
2789 // 16-byte aligned.
2790 nAltivecParamsAtEnd = 0;
2791 for (unsigned i = 0; i != NumOps; ++i) {
2792 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2793 EVT ArgVT = Outs[i].VT;
2794 // Varargs Altivec parameters are padded to a 16 byte boundary.
2795 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2796 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2797 if (!isVarArg && !isPPC64) {
2798 // Non-varargs Altivec parameters go after all the non-Altivec
2799 // parameters; handle those later so we know how much padding we need.
2800 nAltivecParamsAtEnd++;
2801 continue;
2802 }
2803 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2804 NumBytes = ((NumBytes+15)/16)*16;
2805 }
2806 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2807 }
2808
2809 // Allow for Altivec parameters at the end, if needed.
2810 if (nAltivecParamsAtEnd) {
2811 NumBytes = ((NumBytes+15)/16)*16;
2812 NumBytes += 16*nAltivecParamsAtEnd;
2813 }
2814
2815 // The prolog code of the callee may store up to 8 GPR argument registers to
2816 // the stack, allowing va_start to index over them in memory if its varargs.
2817 // Because we cannot tell if this is needed on the caller side, we have to
2818 // conservatively assume that it is needed. As such, make sure we have at
2819 // least enough stack space for the caller to store the 8 GPRs.
2820 NumBytes = std::max(NumBytes,
2821 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2822
2823 // Tail call needs the stack to be aligned.
2824 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2825 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2826 getFrameLowering()->getStackAlignment();
2827 unsigned AlignMask = TargetAlign-1;
2828 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2829 }
2830
2831 return NumBytes;
2832 }
2833
2834 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2835 /// adjusted to accommodate the arguments for the tailcall.
CalculateTailCallSPDiff(SelectionDAG & DAG,bool isTailCall,unsigned ParamSize)2836 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2837 unsigned ParamSize) {
2838
2839 if (!isTailCall) return 0;
2840
2841 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2842 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2843 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2844 // Remember only if the new adjustement is bigger.
2845 if (SPDiff < FI->getTailCallSPDelta())
2846 FI->setTailCallSPDelta(SPDiff);
2847
2848 return SPDiff;
2849 }
2850
2851 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2852 /// for tail call optimization. Targets which want to do tail call
2853 /// optimization should implement this function.
2854 bool
IsEligibleForTailCallOptimization(SDValue Callee,CallingConv::ID CalleeCC,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SelectionDAG & DAG) const2855 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2856 CallingConv::ID CalleeCC,
2857 bool isVarArg,
2858 const SmallVectorImpl<ISD::InputArg> &Ins,
2859 SelectionDAG& DAG) const {
2860 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2861 return false;
2862
2863 // Variable argument functions are not supported.
2864 if (isVarArg)
2865 return false;
2866
2867 MachineFunction &MF = DAG.getMachineFunction();
2868 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2869 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2870 // Functions containing by val parameters are not supported.
2871 for (unsigned i = 0; i != Ins.size(); i++) {
2872 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2873 if (Flags.isByVal()) return false;
2874 }
2875
2876 // Non PIC/GOT tail calls are supported.
2877 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2878 return true;
2879
2880 // At the moment we can only do local tail calls (in same module, hidden
2881 // or protected) if we are generating PIC.
2882 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2883 return G->getGlobal()->hasHiddenVisibility()
2884 || G->getGlobal()->hasProtectedVisibility();
2885 }
2886
2887 return false;
2888 }
2889
2890 /// isCallCompatibleAddress - Return the immediate to use if the specified
2891 /// 32-bit value is representable in the immediate field of a BxA instruction.
isBLACompatibleAddress(SDValue Op,SelectionDAG & DAG)2892 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2893 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2894 if (!C) return 0;
2895
2896 int Addr = C->getZExtValue();
2897 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2898 SignExtend32<26>(Addr) != Addr)
2899 return 0; // Top 6 bits have to be sext of immediate.
2900
2901 return DAG.getConstant((int)C->getZExtValue() >> 2,
2902 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2903 }
2904
2905 namespace {
2906
2907 struct TailCallArgumentInfo {
2908 SDValue Arg;
2909 SDValue FrameIdxOp;
2910 int FrameIdx;
2911
TailCallArgumentInfo__anon323207b40111::TailCallArgumentInfo2912 TailCallArgumentInfo() : FrameIdx(0) {}
2913 };
2914
2915 }
2916
2917 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2918 static void
StoreTailCallArgumentsToStackSlot(SelectionDAG & DAG,SDValue Chain,const SmallVector<TailCallArgumentInfo,8> & TailCallArgs,SmallVector<SDValue,8> & MemOpChains,DebugLoc dl)2919 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2920 SDValue Chain,
2921 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2922 SmallVector<SDValue, 8> &MemOpChains,
2923 DebugLoc dl) {
2924 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2925 SDValue Arg = TailCallArgs[i].Arg;
2926 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2927 int FI = TailCallArgs[i].FrameIdx;
2928 // Store relative to framepointer.
2929 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2930 MachinePointerInfo::getFixedStack(FI),
2931 false, false, 0));
2932 }
2933 }
2934
2935 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2936 /// the appropriate stack slot for the tail call optimized function call.
EmitTailCallStoreFPAndRetAddr(SelectionDAG & DAG,MachineFunction & MF,SDValue Chain,SDValue OldRetAddr,SDValue OldFP,int SPDiff,bool isPPC64,bool isDarwinABI,DebugLoc dl)2937 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2938 MachineFunction &MF,
2939 SDValue Chain,
2940 SDValue OldRetAddr,
2941 SDValue OldFP,
2942 int SPDiff,
2943 bool isPPC64,
2944 bool isDarwinABI,
2945 DebugLoc dl) {
2946 if (SPDiff) {
2947 // Calculate the new stack slot for the return address.
2948 int SlotSize = isPPC64 ? 8 : 4;
2949 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2950 isDarwinABI);
2951 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2952 NewRetAddrLoc, true);
2953 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2954 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2955 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2956 MachinePointerInfo::getFixedStack(NewRetAddr),
2957 false, false, 0);
2958
2959 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2960 // slot as the FP is never overwritten.
2961 if (isDarwinABI) {
2962 int NewFPLoc =
2963 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2964 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2965 true);
2966 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2967 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2968 MachinePointerInfo::getFixedStack(NewFPIdx),
2969 false, false, 0);
2970 }
2971 }
2972 return Chain;
2973 }
2974
2975 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2976 /// the position of the argument.
2977 static void
CalculateTailCallArgDest(SelectionDAG & DAG,MachineFunction & MF,bool isPPC64,SDValue Arg,int SPDiff,unsigned ArgOffset,SmallVector<TailCallArgumentInfo,8> & TailCallArguments)2978 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2979 SDValue Arg, int SPDiff, unsigned ArgOffset,
2980 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2981 int Offset = ArgOffset + SPDiff;
2982 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2983 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2984 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2985 SDValue FIN = DAG.getFrameIndex(FI, VT);
2986 TailCallArgumentInfo Info;
2987 Info.Arg = Arg;
2988 Info.FrameIdxOp = FIN;
2989 Info.FrameIdx = FI;
2990 TailCallArguments.push_back(Info);
2991 }
2992
2993 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2994 /// stack slot. Returns the chain as result and the loaded frame pointers in
2995 /// LROpOut/FPOpout. Used when tail calling.
EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,int SPDiff,SDValue Chain,SDValue & LROpOut,SDValue & FPOpOut,bool isDarwinABI,DebugLoc dl) const2996 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2997 int SPDiff,
2998 SDValue Chain,
2999 SDValue &LROpOut,
3000 SDValue &FPOpOut,
3001 bool isDarwinABI,
3002 DebugLoc dl) const {
3003 if (SPDiff) {
3004 // Load the LR and FP stack slot for later adjusting.
3005 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3006 LROpOut = getReturnAddrFrameIndex(DAG);
3007 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3008 false, false, false, 0);
3009 Chain = SDValue(LROpOut.getNode(), 1);
3010
3011 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3012 // slot as the FP is never overwritten.
3013 if (isDarwinABI) {
3014 FPOpOut = getFramePointerFrameIndex(DAG);
3015 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3016 false, false, false, 0);
3017 Chain = SDValue(FPOpOut.getNode(), 1);
3018 }
3019 }
3020 return Chain;
3021 }
3022
3023 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3024 /// by "Src" to address "Dst" of size "Size". Alignment information is
3025 /// specified by the specific parameter attribute. The copy will be passed as
3026 /// a byval function parameter.
3027 /// Sometimes what we are copying is the end of a larger object, the part that
3028 /// does not fit in registers.
3029 static SDValue
CreateCopyOfByValArgument(SDValue Src,SDValue Dst,SDValue Chain,ISD::ArgFlagsTy Flags,SelectionDAG & DAG,DebugLoc dl)3030 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3031 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3032 DebugLoc dl) {
3033 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3034 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3035 false, false, MachinePointerInfo(0),
3036 MachinePointerInfo(0));
3037 }
3038
3039 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3040 /// tail calls.
3041 static void
LowerMemOpCallTo(SelectionDAG & DAG,MachineFunction & MF,SDValue Chain,SDValue Arg,SDValue PtrOff,int SPDiff,unsigned ArgOffset,bool isPPC64,bool isTailCall,bool isVector,SmallVector<SDValue,8> & MemOpChains,SmallVector<TailCallArgumentInfo,8> & TailCallArguments,DebugLoc dl)3042 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3043 SDValue Arg, SDValue PtrOff, int SPDiff,
3044 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3045 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3046 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3047 DebugLoc dl) {
3048 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3049 if (!isTailCall) {
3050 if (isVector) {
3051 SDValue StackPtr;
3052 if (isPPC64)
3053 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3054 else
3055 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3056 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3057 DAG.getConstant(ArgOffset, PtrVT));
3058 }
3059 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3060 MachinePointerInfo(), false, false, 0));
3061 // Calculate and remember argument location.
3062 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3063 TailCallArguments);
3064 }
3065
3066 static
PrepareTailCall(SelectionDAG & DAG,SDValue & InFlag,SDValue & Chain,DebugLoc dl,bool isPPC64,int SPDiff,unsigned NumBytes,SDValue LROp,SDValue FPOp,bool isDarwinABI,SmallVector<TailCallArgumentInfo,8> & TailCallArguments)3067 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3068 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3069 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3070 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3071 MachineFunction &MF = DAG.getMachineFunction();
3072
3073 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3074 // might overwrite each other in case of tail call optimization.
3075 SmallVector<SDValue, 8> MemOpChains2;
3076 // Do not flag preceding copytoreg stuff together with the following stuff.
3077 InFlag = SDValue();
3078 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3079 MemOpChains2, dl);
3080 if (!MemOpChains2.empty())
3081 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3082 &MemOpChains2[0], MemOpChains2.size());
3083
3084 // Store the return address to the appropriate stack slot.
3085 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3086 isPPC64, isDarwinABI, dl);
3087
3088 // Emit callseq_end just before tailcall node.
3089 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3090 DAG.getIntPtrConstant(0, true), InFlag);
3091 InFlag = Chain.getValue(1);
3092 }
3093
3094 static
PrepareCall(SelectionDAG & DAG,SDValue & Callee,SDValue & InFlag,SDValue & Chain,DebugLoc dl,int SPDiff,bool isTailCall,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SmallVector<SDValue,8> & Ops,std::vector<EVT> & NodeTys,const PPCSubtarget & PPCSubTarget)3095 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3096 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3097 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3098 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3099 const PPCSubtarget &PPCSubTarget) {
3100
3101 bool isPPC64 = PPCSubTarget.isPPC64();
3102 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3103
3104 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3105 NodeTys.push_back(MVT::Other); // Returns a chain
3106 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3107
3108 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
3109
3110 bool needIndirectCall = true;
3111 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3112 // If this is an absolute destination address, use the munged value.
3113 Callee = SDValue(Dest, 0);
3114 needIndirectCall = false;
3115 }
3116
3117 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3118 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3119 // Use indirect calls for ALL functions calls in JIT mode, since the
3120 // far-call stubs may be outside relocation limits for a BL instruction.
3121 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3122 unsigned OpFlags = 0;
3123 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3124 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3125 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3126 (G->getGlobal()->isDeclaration() ||
3127 G->getGlobal()->isWeakForLinker())) {
3128 // PC-relative references to external symbols should go through $stub,
3129 // unless we're building with the leopard linker or later, which
3130 // automatically synthesizes these stubs.
3131 OpFlags = PPCII::MO_DARWIN_STUB;
3132 }
3133
3134 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3135 // every direct call is) turn it into a TargetGlobalAddress /
3136 // TargetExternalSymbol node so that legalize doesn't hack it.
3137 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3138 Callee.getValueType(),
3139 0, OpFlags);
3140 needIndirectCall = false;
3141 }
3142 }
3143
3144 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3145 unsigned char OpFlags = 0;
3146
3147 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3148 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3149 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3150 // PC-relative references to external symbols should go through $stub,
3151 // unless we're building with the leopard linker or later, which
3152 // automatically synthesizes these stubs.
3153 OpFlags = PPCII::MO_DARWIN_STUB;
3154 }
3155
3156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3157 OpFlags);
3158 needIndirectCall = false;
3159 }
3160
3161 if (needIndirectCall) {
3162 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3163 // to do the call, we can't use PPCISD::CALL.
3164 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3165
3166 if (isSVR4ABI && isPPC64) {
3167 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3168 // entry point, but to the function descriptor (the function entry point
3169 // address is part of the function descriptor though).
3170 // The function descriptor is a three doubleword structure with the
3171 // following fields: function entry point, TOC base address and
3172 // environment pointer.
3173 // Thus for a call through a function pointer, the following actions need
3174 // to be performed:
3175 // 1. Save the TOC of the caller in the TOC save area of its stack
3176 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3177 // 2. Load the address of the function entry point from the function
3178 // descriptor.
3179 // 3. Load the TOC of the callee from the function descriptor into r2.
3180 // 4. Load the environment pointer from the function descriptor into
3181 // r11.
3182 // 5. Branch to the function entry point address.
3183 // 6. On return of the callee, the TOC of the caller needs to be
3184 // restored (this is done in FinishCall()).
3185 //
3186 // All those operations are flagged together to ensure that no other
3187 // operations can be scheduled in between. E.g. without flagging the
3188 // operations together, a TOC access in the caller could be scheduled
3189 // between the load of the callee TOC and the branch to the callee, which
3190 // results in the TOC access going through the TOC of the callee instead
3191 // of going through the TOC of the caller, which leads to incorrect code.
3192
3193 // Load the address of the function entry point from the function
3194 // descriptor.
3195 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3196 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3197 InFlag.getNode() ? 3 : 2);
3198 Chain = LoadFuncPtr.getValue(1);
3199 InFlag = LoadFuncPtr.getValue(2);
3200
3201 // Load environment pointer into r11.
3202 // Offset of the environment pointer within the function descriptor.
3203 SDValue PtrOff = DAG.getIntPtrConstant(16);
3204
3205 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3206 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3207 InFlag);
3208 Chain = LoadEnvPtr.getValue(1);
3209 InFlag = LoadEnvPtr.getValue(2);
3210
3211 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3212 InFlag);
3213 Chain = EnvVal.getValue(0);
3214 InFlag = EnvVal.getValue(1);
3215
3216 // Load TOC of the callee into r2. We are using a target-specific load
3217 // with r2 hard coded, because the result of a target-independent load
3218 // would never go directly into r2, since r2 is a reserved register (which
3219 // prevents the register allocator from allocating it), resulting in an
3220 // additional register being allocated and an unnecessary move instruction
3221 // being generated.
3222 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3223 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3224 Callee, InFlag);
3225 Chain = LoadTOCPtr.getValue(0);
3226 InFlag = LoadTOCPtr.getValue(1);
3227
3228 MTCTROps[0] = Chain;
3229 MTCTROps[1] = LoadFuncPtr;
3230 MTCTROps[2] = InFlag;
3231 }
3232
3233 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3234 2 + (InFlag.getNode() != 0));
3235 InFlag = Chain.getValue(1);
3236
3237 NodeTys.clear();
3238 NodeTys.push_back(MVT::Other);
3239 NodeTys.push_back(MVT::Glue);
3240 Ops.push_back(Chain);
3241 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
3242 Callee.setNode(0);
3243 // Add CTR register as callee so a bctr can be emitted later.
3244 if (isTailCall)
3245 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3246 }
3247
3248 // If this is a direct call, pass the chain and the callee.
3249 if (Callee.getNode()) {
3250 Ops.push_back(Chain);
3251 Ops.push_back(Callee);
3252 }
3253 // If this is a tail call add stack pointer delta.
3254 if (isTailCall)
3255 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3256
3257 // Add argument registers to the end of the list so that they are known live
3258 // into the call.
3259 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3260 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3261 RegsToPass[i].second.getValueType()));
3262
3263 return CallOpc;
3264 }
3265
3266 static
isLocalCall(const SDValue & Callee)3267 bool isLocalCall(const SDValue &Callee)
3268 {
3269 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3270 return !G->getGlobal()->isDeclaration() &&
3271 !G->getGlobal()->isWeakForLinker();
3272 return false;
3273 }
3274
3275 SDValue
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const3276 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3277 CallingConv::ID CallConv, bool isVarArg,
3278 const SmallVectorImpl<ISD::InputArg> &Ins,
3279 DebugLoc dl, SelectionDAG &DAG,
3280 SmallVectorImpl<SDValue> &InVals) const {
3281
3282 SmallVector<CCValAssign, 16> RVLocs;
3283 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3284 getTargetMachine(), RVLocs, *DAG.getContext());
3285 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3286
3287 // Copy all of the result registers out of their specified physreg.
3288 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3289 CCValAssign &VA = RVLocs[i];
3290 assert(VA.isRegLoc() && "Can only return in registers!");
3291
3292 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3293 VA.getLocReg(), VA.getLocVT(), InFlag);
3294 Chain = Val.getValue(1);
3295 InFlag = Val.getValue(2);
3296
3297 switch (VA.getLocInfo()) {
3298 default: llvm_unreachable("Unknown loc info!");
3299 case CCValAssign::Full: break;
3300 case CCValAssign::AExt:
3301 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3302 break;
3303 case CCValAssign::ZExt:
3304 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3305 DAG.getValueType(VA.getValVT()));
3306 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3307 break;
3308 case CCValAssign::SExt:
3309 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3310 DAG.getValueType(VA.getValVT()));
3311 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3312 break;
3313 }
3314
3315 InVals.push_back(Val);
3316 }
3317
3318 return Chain;
3319 }
3320
3321 SDValue
FinishCall(CallingConv::ID CallConv,DebugLoc dl,bool isTailCall,bool isVarArg,SelectionDAG & DAG,SmallVector<std::pair<unsigned,SDValue>,8> & RegsToPass,SDValue InFlag,SDValue Chain,SDValue & Callee,int SPDiff,unsigned NumBytes,const SmallVectorImpl<ISD::InputArg> & Ins,SmallVectorImpl<SDValue> & InVals) const3322 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3323 bool isTailCall, bool isVarArg,
3324 SelectionDAG &DAG,
3325 SmallVector<std::pair<unsigned, SDValue>, 8>
3326 &RegsToPass,
3327 SDValue InFlag, SDValue Chain,
3328 SDValue &Callee,
3329 int SPDiff, unsigned NumBytes,
3330 const SmallVectorImpl<ISD::InputArg> &Ins,
3331 SmallVectorImpl<SDValue> &InVals) const {
3332 std::vector<EVT> NodeTys;
3333 SmallVector<SDValue, 8> Ops;
3334 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3335 isTailCall, RegsToPass, Ops, NodeTys,
3336 PPCSubTarget);
3337
3338 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3339 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3340 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3341
3342 // When performing tail call optimization the callee pops its arguments off
3343 // the stack. Account for this here so these bytes can be pushed back on in
3344 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3345 int BytesCalleePops =
3346 (CallConv == CallingConv::Fast &&
3347 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3348
3349 // Add a register mask operand representing the call-preserved registers.
3350 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3351 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3352 assert(Mask && "Missing call preserved mask for calling convention");
3353 Ops.push_back(DAG.getRegisterMask(Mask));
3354
3355 if (InFlag.getNode())
3356 Ops.push_back(InFlag);
3357
3358 // Emit tail call.
3359 if (isTailCall) {
3360 assert(((Callee.getOpcode() == ISD::Register &&
3361 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3362 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3363 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3364 isa<ConstantSDNode>(Callee)) &&
3365 "Expecting an global address, external symbol, absolute value or register");
3366
3367 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3368 }
3369
3370 // Add a NOP immediately after the branch instruction when using the 64-bit
3371 // SVR4 ABI. At link time, if caller and callee are in a different module and
3372 // thus have a different TOC, the call will be replaced with a call to a stub
3373 // function which saves the current TOC, loads the TOC of the callee and
3374 // branches to the callee. The NOP will be replaced with a load instruction
3375 // which restores the TOC of the caller from the TOC save slot of the current
3376 // stack frame. If caller and callee belong to the same module (and have the
3377 // same TOC), the NOP will remain unchanged.
3378
3379 bool needsTOCRestore = false;
3380 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3381 if (CallOpc == PPCISD::BCTRL_SVR4) {
3382 // This is a call through a function pointer.
3383 // Restore the caller TOC from the save area into R2.
3384 // See PrepareCall() for more information about calls through function
3385 // pointers in the 64-bit SVR4 ABI.
3386 // We are using a target-specific load with r2 hard coded, because the
3387 // result of a target-independent load would never go directly into r2,
3388 // since r2 is a reserved register (which prevents the register allocator
3389 // from allocating it), resulting in an additional register being
3390 // allocated and an unnecessary move instruction being generated.
3391 needsTOCRestore = true;
3392 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) {
3393 // Otherwise insert NOP for non-local calls.
3394 CallOpc = PPCISD::CALL_NOP_SVR4;
3395 }
3396 }
3397
3398 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3399 InFlag = Chain.getValue(1);
3400
3401 if (needsTOCRestore) {
3402 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3403 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3404 InFlag = Chain.getValue(1);
3405 }
3406
3407 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3408 DAG.getIntPtrConstant(BytesCalleePops, true),
3409 InFlag);
3410 if (!Ins.empty())
3411 InFlag = Chain.getValue(1);
3412
3413 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3414 Ins, dl, DAG, InVals);
3415 }
3416
3417 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const3418 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3419 SmallVectorImpl<SDValue> &InVals) const {
3420 SelectionDAG &DAG = CLI.DAG;
3421 DebugLoc &dl = CLI.DL;
3422 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3423 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3424 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3425 SDValue Chain = CLI.Chain;
3426 SDValue Callee = CLI.Callee;
3427 bool &isTailCall = CLI.IsTailCall;
3428 CallingConv::ID CallConv = CLI.CallConv;
3429 bool isVarArg = CLI.IsVarArg;
3430
3431 if (isTailCall)
3432 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3433 Ins, DAG);
3434
3435 if (PPCSubTarget.isSVR4ABI()) {
3436 if (PPCSubTarget.isPPC64())
3437 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3438 isTailCall, Outs, OutVals, Ins,
3439 dl, DAG, InVals);
3440 else
3441 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3442 isTailCall, Outs, OutVals, Ins,
3443 dl, DAG, InVals);
3444 }
3445
3446 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3447 isTailCall, Outs, OutVals, Ins,
3448 dl, DAG, InVals);
3449 }
3450
3451 SDValue
LowerCall_32SVR4(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const3452 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3453 CallingConv::ID CallConv, bool isVarArg,
3454 bool isTailCall,
3455 const SmallVectorImpl<ISD::OutputArg> &Outs,
3456 const SmallVectorImpl<SDValue> &OutVals,
3457 const SmallVectorImpl<ISD::InputArg> &Ins,
3458 DebugLoc dl, SelectionDAG &DAG,
3459 SmallVectorImpl<SDValue> &InVals) const {
3460 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3461 // of the 32-bit SVR4 ABI stack frame layout.
3462
3463 assert((CallConv == CallingConv::C ||
3464 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3465
3466 unsigned PtrByteSize = 4;
3467
3468 MachineFunction &MF = DAG.getMachineFunction();
3469
3470 // Mark this function as potentially containing a function that contains a
3471 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3472 // and restoring the callers stack pointer in this functions epilog. This is
3473 // done because by tail calling the called function might overwrite the value
3474 // in this function's (MF) stack pointer stack slot 0(SP).
3475 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3476 CallConv == CallingConv::Fast)
3477 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3478
3479 // Count how many bytes are to be pushed on the stack, including the linkage
3480 // area, parameter list area and the part of the local variable space which
3481 // contains copies of aggregates which are passed by value.
3482
3483 // Assign locations to all of the outgoing arguments.
3484 SmallVector<CCValAssign, 16> ArgLocs;
3485 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3486 getTargetMachine(), ArgLocs, *DAG.getContext());
3487
3488 // Reserve space for the linkage area on the stack.
3489 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3490
3491 if (isVarArg) {
3492 // Handle fixed and variable vector arguments differently.
3493 // Fixed vector arguments go into registers as long as registers are
3494 // available. Variable vector arguments always go into memory.
3495 unsigned NumArgs = Outs.size();
3496
3497 for (unsigned i = 0; i != NumArgs; ++i) {
3498 MVT ArgVT = Outs[i].VT;
3499 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3500 bool Result;
3501
3502 if (Outs[i].IsFixed) {
3503 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3504 CCInfo);
3505 } else {
3506 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3507 ArgFlags, CCInfo);
3508 }
3509
3510 if (Result) {
3511 #ifndef NDEBUG
3512 errs() << "Call operand #" << i << " has unhandled type "
3513 << EVT(ArgVT).getEVTString() << "\n";
3514 #endif
3515 llvm_unreachable(0);
3516 }
3517 }
3518 } else {
3519 // All arguments are treated the same.
3520 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3521 }
3522
3523 // Assign locations to all of the outgoing aggregate by value arguments.
3524 SmallVector<CCValAssign, 16> ByValArgLocs;
3525 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3526 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3527
3528 // Reserve stack space for the allocations in CCInfo.
3529 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3530
3531 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3532
3533 // Size of the linkage area, parameter list area and the part of the local
3534 // space variable where copies of aggregates which are passed by value are
3535 // stored.
3536 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3537
3538 // Calculate by how many bytes the stack has to be adjusted in case of tail
3539 // call optimization.
3540 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3541
3542 // Adjust the stack pointer for the new arguments...
3543 // These operations are automatically eliminated by the prolog/epilog pass
3544 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3545 SDValue CallSeqStart = Chain;
3546
3547 // Load the return address and frame pointer so it can be moved somewhere else
3548 // later.
3549 SDValue LROp, FPOp;
3550 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3551 dl);
3552
3553 // Set up a copy of the stack pointer for use loading and storing any
3554 // arguments that may not fit in the registers available for argument
3555 // passing.
3556 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3557
3558 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3559 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3560 SmallVector<SDValue, 8> MemOpChains;
3561
3562 bool seenFloatArg = false;
3563 // Walk the register/memloc assignments, inserting copies/loads.
3564 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3565 i != e;
3566 ++i) {
3567 CCValAssign &VA = ArgLocs[i];
3568 SDValue Arg = OutVals[i];
3569 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3570
3571 if (Flags.isByVal()) {
3572 // Argument is an aggregate which is passed by value, thus we need to
3573 // create a copy of it in the local variable space of the current stack
3574 // frame (which is the stack frame of the caller) and pass the address of
3575 // this copy to the callee.
3576 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3577 CCValAssign &ByValVA = ByValArgLocs[j++];
3578 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3579
3580 // Memory reserved in the local variable space of the callers stack frame.
3581 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3582
3583 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3584 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3585
3586 // Create a copy of the argument in the local area of the current
3587 // stack frame.
3588 SDValue MemcpyCall =
3589 CreateCopyOfByValArgument(Arg, PtrOff,
3590 CallSeqStart.getNode()->getOperand(0),
3591 Flags, DAG, dl);
3592
3593 // This must go outside the CALLSEQ_START..END.
3594 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3595 CallSeqStart.getNode()->getOperand(1));
3596 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3597 NewCallSeqStart.getNode());
3598 Chain = CallSeqStart = NewCallSeqStart;
3599
3600 // Pass the address of the aggregate copy on the stack either in a
3601 // physical register or in the parameter list area of the current stack
3602 // frame to the callee.
3603 Arg = PtrOff;
3604 }
3605
3606 if (VA.isRegLoc()) {
3607 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3608 // Put argument in a physical register.
3609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3610 } else {
3611 // Put argument in the parameter list area of the current stack frame.
3612 assert(VA.isMemLoc());
3613 unsigned LocMemOffset = VA.getLocMemOffset();
3614
3615 if (!isTailCall) {
3616 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3617 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3618
3619 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3620 MachinePointerInfo(),
3621 false, false, 0));
3622 } else {
3623 // Calculate and remember argument location.
3624 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3625 TailCallArguments);
3626 }
3627 }
3628 }
3629
3630 if (!MemOpChains.empty())
3631 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3632 &MemOpChains[0], MemOpChains.size());
3633
3634 // Build a sequence of copy-to-reg nodes chained together with token chain
3635 // and flag operands which copy the outgoing args into the appropriate regs.
3636 SDValue InFlag;
3637 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3638 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3639 RegsToPass[i].second, InFlag);
3640 InFlag = Chain.getValue(1);
3641 }
3642
3643 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3644 // registers.
3645 if (isVarArg) {
3646 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3647 SDValue Ops[] = { Chain, InFlag };
3648
3649 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3650 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3651
3652 InFlag = Chain.getValue(1);
3653 }
3654
3655 if (isTailCall)
3656 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3657 false, TailCallArguments);
3658
3659 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3660 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3661 Ins, InVals);
3662 }
3663
3664 // Copy an argument into memory, being careful to do this outside the
3665 // call sequence for the call to which the argument belongs.
3666 SDValue
createMemcpyOutsideCallSeq(SDValue Arg,SDValue PtrOff,SDValue CallSeqStart,ISD::ArgFlagsTy Flags,SelectionDAG & DAG,DebugLoc dl) const3667 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3668 SDValue CallSeqStart,
3669 ISD::ArgFlagsTy Flags,
3670 SelectionDAG &DAG,
3671 DebugLoc dl) const {
3672 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3673 CallSeqStart.getNode()->getOperand(0),
3674 Flags, DAG, dl);
3675 // The MEMCPY must go outside the CALLSEQ_START..END.
3676 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3677 CallSeqStart.getNode()->getOperand(1));
3678 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3679 NewCallSeqStart.getNode());
3680 return NewCallSeqStart;
3681 }
3682
3683 SDValue
LowerCall_64SVR4(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const3684 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3685 CallingConv::ID CallConv, bool isVarArg,
3686 bool isTailCall,
3687 const SmallVectorImpl<ISD::OutputArg> &Outs,
3688 const SmallVectorImpl<SDValue> &OutVals,
3689 const SmallVectorImpl<ISD::InputArg> &Ins,
3690 DebugLoc dl, SelectionDAG &DAG,
3691 SmallVectorImpl<SDValue> &InVals) const {
3692
3693 unsigned NumOps = Outs.size();
3694
3695 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3696 unsigned PtrByteSize = 8;
3697
3698 MachineFunction &MF = DAG.getMachineFunction();
3699
3700 // Mark this function as potentially containing a function that contains a
3701 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3702 // and restoring the callers stack pointer in this functions epilog. This is
3703 // done because by tail calling the called function might overwrite the value
3704 // in this function's (MF) stack pointer stack slot 0(SP).
3705 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3706 CallConv == CallingConv::Fast)
3707 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3708
3709 unsigned nAltivecParamsAtEnd = 0;
3710
3711 // Count how many bytes are to be pushed on the stack, including the linkage
3712 // area, and parameter passing area. We start with at least 48 bytes, which
3713 // is reserved space for [SP][CR][LR][3 x unused].
3714 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3715 // of this call.
3716 unsigned NumBytes =
3717 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3718 Outs, OutVals, nAltivecParamsAtEnd);
3719
3720 // Calculate by how many bytes the stack has to be adjusted in case of tail
3721 // call optimization.
3722 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3723
3724 // To protect arguments on the stack from being clobbered in a tail call,
3725 // force all the loads to happen before doing any other lowering.
3726 if (isTailCall)
3727 Chain = DAG.getStackArgumentTokenFactor(Chain);
3728
3729 // Adjust the stack pointer for the new arguments...
3730 // These operations are automatically eliminated by the prolog/epilog pass
3731 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3732 SDValue CallSeqStart = Chain;
3733
3734 // Load the return address and frame pointer so it can be move somewhere else
3735 // later.
3736 SDValue LROp, FPOp;
3737 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3738 dl);
3739
3740 // Set up a copy of the stack pointer for use loading and storing any
3741 // arguments that may not fit in the registers available for argument
3742 // passing.
3743 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3744
3745 // Figure out which arguments are going to go in registers, and which in
3746 // memory. Also, if this is a vararg function, floating point operations
3747 // must be stored to our stack, and loaded into integer regs as well, if
3748 // any integer regs are available for argument passing.
3749 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3750 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3751
3752 static const uint16_t GPR[] = {
3753 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3754 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3755 };
3756 static const uint16_t *FPR = GetFPR();
3757
3758 static const uint16_t VR[] = {
3759 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3760 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3761 };
3762 const unsigned NumGPRs = array_lengthof(GPR);
3763 const unsigned NumFPRs = 13;
3764 const unsigned NumVRs = array_lengthof(VR);
3765
3766 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3767 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3768
3769 SmallVector<SDValue, 8> MemOpChains;
3770 for (unsigned i = 0; i != NumOps; ++i) {
3771 SDValue Arg = OutVals[i];
3772 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3773
3774 // PtrOff will be used to store the current argument to the stack if a
3775 // register cannot be found for it.
3776 SDValue PtrOff;
3777
3778 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3779
3780 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3781
3782 // Promote integers to 64-bit values.
3783 if (Arg.getValueType() == MVT::i32) {
3784 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3785 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3786 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3787 }
3788
3789 // FIXME memcpy is used way more than necessary. Correctness first.
3790 // Note: "by value" is code for passing a structure by value, not
3791 // basic types.
3792 if (Flags.isByVal()) {
3793 // Note: Size includes alignment padding, so
3794 // struct x { short a; char b; }
3795 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3796 // These are the proper values we need for right-justifying the
3797 // aggregate in a parameter register.
3798 unsigned Size = Flags.getByValSize();
3799
3800 // An empty aggregate parameter takes up no storage and no
3801 // registers.
3802 if (Size == 0)
3803 continue;
3804
3805 // All aggregates smaller than 8 bytes must be passed right-justified.
3806 if (Size==1 || Size==2 || Size==4) {
3807 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3808 if (GPR_idx != NumGPRs) {
3809 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3810 MachinePointerInfo(), VT,
3811 false, false, 0);
3812 MemOpChains.push_back(Load.getValue(1));
3813 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3814
3815 ArgOffset += PtrByteSize;
3816 continue;
3817 }
3818 }
3819
3820 if (GPR_idx == NumGPRs && Size < 8) {
3821 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3822 PtrOff.getValueType());
3823 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3824 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3825 CallSeqStart,
3826 Flags, DAG, dl);
3827 ArgOffset += PtrByteSize;
3828 continue;
3829 }
3830 // Copy entire object into memory. There are cases where gcc-generated
3831 // code assumes it is there, even if it could be put entirely into
3832 // registers. (This is not what the doc says.)
3833
3834 // FIXME: The above statement is likely due to a misunderstanding of the
3835 // documents. All arguments must be copied into the parameter area BY
3836 // THE CALLEE in the event that the callee takes the address of any
3837 // formal argument. That has not yet been implemented. However, it is
3838 // reasonable to use the stack area as a staging area for the register
3839 // load.
3840
3841 // Skip this for small aggregates, as we will use the same slot for a
3842 // right-justified copy, below.
3843 if (Size >= 8)
3844 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3845 CallSeqStart,
3846 Flags, DAG, dl);
3847
3848 // When a register is available, pass a small aggregate right-justified.
3849 if (Size < 8 && GPR_idx != NumGPRs) {
3850 // The easiest way to get this right-justified in a register
3851 // is to copy the structure into the rightmost portion of a
3852 // local variable slot, then load the whole slot into the
3853 // register.
3854 // FIXME: The memcpy seems to produce pretty awful code for
3855 // small aggregates, particularly for packed ones.
3856 // FIXME: It would be preferable to use the slot in the
3857 // parameter save area instead of a new local variable.
3858 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3859 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3860 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3861 CallSeqStart,
3862 Flags, DAG, dl);
3863
3864 // Load the slot into the register.
3865 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3866 MachinePointerInfo(),
3867 false, false, false, 0);
3868 MemOpChains.push_back(Load.getValue(1));
3869 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3870
3871 // Done with this argument.
3872 ArgOffset += PtrByteSize;
3873 continue;
3874 }
3875
3876 // For aggregates larger than PtrByteSize, copy the pieces of the
3877 // object that fit into registers from the parameter save area.
3878 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3879 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3880 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3881 if (GPR_idx != NumGPRs) {
3882 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3883 MachinePointerInfo(),
3884 false, false, false, 0);
3885 MemOpChains.push_back(Load.getValue(1));
3886 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3887 ArgOffset += PtrByteSize;
3888 } else {
3889 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3890 break;
3891 }
3892 }
3893 continue;
3894 }
3895
3896 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3897 default: llvm_unreachable("Unexpected ValueType for argument!");
3898 case MVT::i32:
3899 case MVT::i64:
3900 if (GPR_idx != NumGPRs) {
3901 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3902 } else {
3903 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3904 true, isTailCall, false, MemOpChains,
3905 TailCallArguments, dl);
3906 }
3907 ArgOffset += PtrByteSize;
3908 break;
3909 case MVT::f32:
3910 case MVT::f64:
3911 if (FPR_idx != NumFPRs) {
3912 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3913
3914 if (isVarArg) {
3915 // A single float or an aggregate containing only a single float
3916 // must be passed right-justified in the stack doubleword, and
3917 // in the GPR, if one is available.
3918 SDValue StoreOff;
3919 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3920 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3921 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3922 } else
3923 StoreOff = PtrOff;
3924
3925 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3926 MachinePointerInfo(), false, false, 0);
3927 MemOpChains.push_back(Store);
3928
3929 // Float varargs are always shadowed in available integer registers
3930 if (GPR_idx != NumGPRs) {
3931 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3932 MachinePointerInfo(), false, false,
3933 false, 0);
3934 MemOpChains.push_back(Load.getValue(1));
3935 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3936 }
3937 } else if (GPR_idx != NumGPRs)
3938 // If we have any FPRs remaining, we may also have GPRs remaining.
3939 ++GPR_idx;
3940 } else {
3941 // Single-precision floating-point values are mapped to the
3942 // second (rightmost) word of the stack doubleword.
3943 if (Arg.getValueType() == MVT::f32) {
3944 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3945 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3946 }
3947
3948 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3949 true, isTailCall, false, MemOpChains,
3950 TailCallArguments, dl);
3951 }
3952 ArgOffset += 8;
3953 break;
3954 case MVT::v4f32:
3955 case MVT::v4i32:
3956 case MVT::v8i16:
3957 case MVT::v16i8:
3958 if (isVarArg) {
3959 // These go aligned on the stack, or in the corresponding R registers
3960 // when within range. The Darwin PPC ABI doc claims they also go in
3961 // V registers; in fact gcc does this only for arguments that are
3962 // prototyped, not for those that match the ... We do it for all
3963 // arguments, seems to work.
3964 while (ArgOffset % 16 !=0) {
3965 ArgOffset += PtrByteSize;
3966 if (GPR_idx != NumGPRs)
3967 GPR_idx++;
3968 }
3969 // We could elide this store in the case where the object fits
3970 // entirely in R registers. Maybe later.
3971 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3972 DAG.getConstant(ArgOffset, PtrVT));
3973 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3974 MachinePointerInfo(), false, false, 0);
3975 MemOpChains.push_back(Store);
3976 if (VR_idx != NumVRs) {
3977 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3978 MachinePointerInfo(),
3979 false, false, false, 0);
3980 MemOpChains.push_back(Load.getValue(1));
3981 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3982 }
3983 ArgOffset += 16;
3984 for (unsigned i=0; i<16; i+=PtrByteSize) {
3985 if (GPR_idx == NumGPRs)
3986 break;
3987 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3988 DAG.getConstant(i, PtrVT));
3989 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3990 false, false, false, 0);
3991 MemOpChains.push_back(Load.getValue(1));
3992 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3993 }
3994 break;
3995 }
3996
3997 // Non-varargs Altivec params generally go in registers, but have
3998 // stack space allocated at the end.
3999 if (VR_idx != NumVRs) {
4000 // Doesn't have GPR space allocated.
4001 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4002 } else {
4003 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4004 true, isTailCall, true, MemOpChains,
4005 TailCallArguments, dl);
4006 ArgOffset += 16;
4007 }
4008 break;
4009 }
4010 }
4011
4012 if (!MemOpChains.empty())
4013 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4014 &MemOpChains[0], MemOpChains.size());
4015
4016 // Check if this is an indirect call (MTCTR/BCTRL).
4017 // See PrepareCall() for more information about calls through function
4018 // pointers in the 64-bit SVR4 ABI.
4019 if (!isTailCall &&
4020 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4021 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4022 !isBLACompatibleAddress(Callee, DAG)) {
4023 // Load r2 into a virtual register and store it to the TOC save area.
4024 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4025 // TOC save area offset.
4026 SDValue PtrOff = DAG.getIntPtrConstant(40);
4027 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4028 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4029 false, false, 0);
4030 // R12 must contain the address of an indirect callee. This does not
4031 // mean the MTCTR instruction must use R12; it's easier to model this
4032 // as an extra parameter, so do that.
4033 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4034 }
4035
4036 // Build a sequence of copy-to-reg nodes chained together with token chain
4037 // and flag operands which copy the outgoing args into the appropriate regs.
4038 SDValue InFlag;
4039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4041 RegsToPass[i].second, InFlag);
4042 InFlag = Chain.getValue(1);
4043 }
4044
4045 if (isTailCall)
4046 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4047 FPOp, true, TailCallArguments);
4048
4049 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4050 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4051 Ins, InVals);
4052 }
4053
4054 SDValue
LowerCall_Darwin(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const4055 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4056 CallingConv::ID CallConv, bool isVarArg,
4057 bool isTailCall,
4058 const SmallVectorImpl<ISD::OutputArg> &Outs,
4059 const SmallVectorImpl<SDValue> &OutVals,
4060 const SmallVectorImpl<ISD::InputArg> &Ins,
4061 DebugLoc dl, SelectionDAG &DAG,
4062 SmallVectorImpl<SDValue> &InVals) const {
4063
4064 unsigned NumOps = Outs.size();
4065
4066 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4067 bool isPPC64 = PtrVT == MVT::i64;
4068 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4069
4070 MachineFunction &MF = DAG.getMachineFunction();
4071
4072 // Mark this function as potentially containing a function that contains a
4073 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4074 // and restoring the callers stack pointer in this functions epilog. This is
4075 // done because by tail calling the called function might overwrite the value
4076 // in this function's (MF) stack pointer stack slot 0(SP).
4077 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4078 CallConv == CallingConv::Fast)
4079 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4080
4081 unsigned nAltivecParamsAtEnd = 0;
4082
4083 // Count how many bytes are to be pushed on the stack, including the linkage
4084 // area, and parameter passing area. We start with 24/48 bytes, which is
4085 // prereserved space for [SP][CR][LR][3 x unused].
4086 unsigned NumBytes =
4087 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4088 Outs, OutVals,
4089 nAltivecParamsAtEnd);
4090
4091 // Calculate by how many bytes the stack has to be adjusted in case of tail
4092 // call optimization.
4093 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4094
4095 // To protect arguments on the stack from being clobbered in a tail call,
4096 // force all the loads to happen before doing any other lowering.
4097 if (isTailCall)
4098 Chain = DAG.getStackArgumentTokenFactor(Chain);
4099
4100 // Adjust the stack pointer for the new arguments...
4101 // These operations are automatically eliminated by the prolog/epilog pass
4102 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4103 SDValue CallSeqStart = Chain;
4104
4105 // Load the return address and frame pointer so it can be move somewhere else
4106 // later.
4107 SDValue LROp, FPOp;
4108 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4109 dl);
4110
4111 // Set up a copy of the stack pointer for use loading and storing any
4112 // arguments that may not fit in the registers available for argument
4113 // passing.
4114 SDValue StackPtr;
4115 if (isPPC64)
4116 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4117 else
4118 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4119
4120 // Figure out which arguments are going to go in registers, and which in
4121 // memory. Also, if this is a vararg function, floating point operations
4122 // must be stored to our stack, and loaded into integer regs as well, if
4123 // any integer regs are available for argument passing.
4124 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4125 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4126
4127 static const uint16_t GPR_32[] = { // 32-bit registers.
4128 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4129 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4130 };
4131 static const uint16_t GPR_64[] = { // 64-bit registers.
4132 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4133 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4134 };
4135 static const uint16_t *FPR = GetFPR();
4136
4137 static const uint16_t VR[] = {
4138 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4139 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4140 };
4141 const unsigned NumGPRs = array_lengthof(GPR_32);
4142 const unsigned NumFPRs = 13;
4143 const unsigned NumVRs = array_lengthof(VR);
4144
4145 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4146
4147 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4148 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4149
4150 SmallVector<SDValue, 8> MemOpChains;
4151 for (unsigned i = 0; i != NumOps; ++i) {
4152 SDValue Arg = OutVals[i];
4153 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4154
4155 // PtrOff will be used to store the current argument to the stack if a
4156 // register cannot be found for it.
4157 SDValue PtrOff;
4158
4159 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4160
4161 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4162
4163 // On PPC64, promote integers to 64-bit values.
4164 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4165 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4166 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4167 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4168 }
4169
4170 // FIXME memcpy is used way more than necessary. Correctness first.
4171 // Note: "by value" is code for passing a structure by value, not
4172 // basic types.
4173 if (Flags.isByVal()) {
4174 unsigned Size = Flags.getByValSize();
4175 // Very small objects are passed right-justified. Everything else is
4176 // passed left-justified.
4177 if (Size==1 || Size==2) {
4178 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4179 if (GPR_idx != NumGPRs) {
4180 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4181 MachinePointerInfo(), VT,
4182 false, false, 0);
4183 MemOpChains.push_back(Load.getValue(1));
4184 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4185
4186 ArgOffset += PtrByteSize;
4187 } else {
4188 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4189 PtrOff.getValueType());
4190 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4191 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4192 CallSeqStart,
4193 Flags, DAG, dl);
4194 ArgOffset += PtrByteSize;
4195 }
4196 continue;
4197 }
4198 // Copy entire object into memory. There are cases where gcc-generated
4199 // code assumes it is there, even if it could be put entirely into
4200 // registers. (This is not what the doc says.)
4201 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4202 CallSeqStart,
4203 Flags, DAG, dl);
4204
4205 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4206 // copy the pieces of the object that fit into registers from the
4207 // parameter save area.
4208 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4209 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4210 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4211 if (GPR_idx != NumGPRs) {
4212 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4213 MachinePointerInfo(),
4214 false, false, false, 0);
4215 MemOpChains.push_back(Load.getValue(1));
4216 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4217 ArgOffset += PtrByteSize;
4218 } else {
4219 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4220 break;
4221 }
4222 }
4223 continue;
4224 }
4225
4226 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4227 default: llvm_unreachable("Unexpected ValueType for argument!");
4228 case MVT::i32:
4229 case MVT::i64:
4230 if (GPR_idx != NumGPRs) {
4231 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4232 } else {
4233 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4234 isPPC64, isTailCall, false, MemOpChains,
4235 TailCallArguments, dl);
4236 }
4237 ArgOffset += PtrByteSize;
4238 break;
4239 case MVT::f32:
4240 case MVT::f64:
4241 if (FPR_idx != NumFPRs) {
4242 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4243
4244 if (isVarArg) {
4245 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4246 MachinePointerInfo(), false, false, 0);
4247 MemOpChains.push_back(Store);
4248
4249 // Float varargs are always shadowed in available integer registers
4250 if (GPR_idx != NumGPRs) {
4251 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4252 MachinePointerInfo(), false, false,
4253 false, 0);
4254 MemOpChains.push_back(Load.getValue(1));
4255 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4256 }
4257 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4258 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4259 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4260 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4261 MachinePointerInfo(),
4262 false, false, false, 0);
4263 MemOpChains.push_back(Load.getValue(1));
4264 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4265 }
4266 } else {
4267 // If we have any FPRs remaining, we may also have GPRs remaining.
4268 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4269 // GPRs.
4270 if (GPR_idx != NumGPRs)
4271 ++GPR_idx;
4272 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4273 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4274 ++GPR_idx;
4275 }
4276 } else
4277 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4278 isPPC64, isTailCall, false, MemOpChains,
4279 TailCallArguments, dl);
4280 if (isPPC64)
4281 ArgOffset += 8;
4282 else
4283 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4284 break;
4285 case MVT::v4f32:
4286 case MVT::v4i32:
4287 case MVT::v8i16:
4288 case MVT::v16i8:
4289 if (isVarArg) {
4290 // These go aligned on the stack, or in the corresponding R registers
4291 // when within range. The Darwin PPC ABI doc claims they also go in
4292 // V registers; in fact gcc does this only for arguments that are
4293 // prototyped, not for those that match the ... We do it for all
4294 // arguments, seems to work.
4295 while (ArgOffset % 16 !=0) {
4296 ArgOffset += PtrByteSize;
4297 if (GPR_idx != NumGPRs)
4298 GPR_idx++;
4299 }
4300 // We could elide this store in the case where the object fits
4301 // entirely in R registers. Maybe later.
4302 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4303 DAG.getConstant(ArgOffset, PtrVT));
4304 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4305 MachinePointerInfo(), false, false, 0);
4306 MemOpChains.push_back(Store);
4307 if (VR_idx != NumVRs) {
4308 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4309 MachinePointerInfo(),
4310 false, false, false, 0);
4311 MemOpChains.push_back(Load.getValue(1));
4312 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4313 }
4314 ArgOffset += 16;
4315 for (unsigned i=0; i<16; i+=PtrByteSize) {
4316 if (GPR_idx == NumGPRs)
4317 break;
4318 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4319 DAG.getConstant(i, PtrVT));
4320 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4321 false, false, false, 0);
4322 MemOpChains.push_back(Load.getValue(1));
4323 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4324 }
4325 break;
4326 }
4327
4328 // Non-varargs Altivec params generally go in registers, but have
4329 // stack space allocated at the end.
4330 if (VR_idx != NumVRs) {
4331 // Doesn't have GPR space allocated.
4332 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4333 } else if (nAltivecParamsAtEnd==0) {
4334 // We are emitting Altivec params in order.
4335 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4336 isPPC64, isTailCall, true, MemOpChains,
4337 TailCallArguments, dl);
4338 ArgOffset += 16;
4339 }
4340 break;
4341 }
4342 }
4343 // If all Altivec parameters fit in registers, as they usually do,
4344 // they get stack space following the non-Altivec parameters. We
4345 // don't track this here because nobody below needs it.
4346 // If there are more Altivec parameters than fit in registers emit
4347 // the stores here.
4348 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4349 unsigned j = 0;
4350 // Offset is aligned; skip 1st 12 params which go in V registers.
4351 ArgOffset = ((ArgOffset+15)/16)*16;
4352 ArgOffset += 12*16;
4353 for (unsigned i = 0; i != NumOps; ++i) {
4354 SDValue Arg = OutVals[i];
4355 EVT ArgType = Outs[i].VT;
4356 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4357 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4358 if (++j > NumVRs) {
4359 SDValue PtrOff;
4360 // We are emitting Altivec params in order.
4361 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4362 isPPC64, isTailCall, true, MemOpChains,
4363 TailCallArguments, dl);
4364 ArgOffset += 16;
4365 }
4366 }
4367 }
4368 }
4369
4370 if (!MemOpChains.empty())
4371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4372 &MemOpChains[0], MemOpChains.size());
4373
4374 // On Darwin, R12 must contain the address of an indirect callee. This does
4375 // not mean the MTCTR instruction must use R12; it's easier to model this as
4376 // an extra parameter, so do that.
4377 if (!isTailCall &&
4378 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4379 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4380 !isBLACompatibleAddress(Callee, DAG))
4381 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4382 PPC::R12), Callee));
4383
4384 // Build a sequence of copy-to-reg nodes chained together with token chain
4385 // and flag operands which copy the outgoing args into the appropriate regs.
4386 SDValue InFlag;
4387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4388 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4389 RegsToPass[i].second, InFlag);
4390 InFlag = Chain.getValue(1);
4391 }
4392
4393 if (isTailCall)
4394 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4395 FPOp, true, TailCallArguments);
4396
4397 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4398 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4399 Ins, InVals);
4400 }
4401
4402 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const4403 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4404 MachineFunction &MF, bool isVarArg,
4405 const SmallVectorImpl<ISD::OutputArg> &Outs,
4406 LLVMContext &Context) const {
4407 SmallVector<CCValAssign, 16> RVLocs;
4408 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4409 RVLocs, Context);
4410 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4411 }
4412
4413 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,DebugLoc dl,SelectionDAG & DAG) const4414 PPCTargetLowering::LowerReturn(SDValue Chain,
4415 CallingConv::ID CallConv, bool isVarArg,
4416 const SmallVectorImpl<ISD::OutputArg> &Outs,
4417 const SmallVectorImpl<SDValue> &OutVals,
4418 DebugLoc dl, SelectionDAG &DAG) const {
4419
4420 SmallVector<CCValAssign, 16> RVLocs;
4421 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4422 getTargetMachine(), RVLocs, *DAG.getContext());
4423 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4424
4425 SDValue Flag;
4426 SmallVector<SDValue, 4> RetOps(1, Chain);
4427
4428 // Copy the result values into the output registers.
4429 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4430 CCValAssign &VA = RVLocs[i];
4431 assert(VA.isRegLoc() && "Can only return in registers!");
4432
4433 SDValue Arg = OutVals[i];
4434
4435 switch (VA.getLocInfo()) {
4436 default: llvm_unreachable("Unknown loc info!");
4437 case CCValAssign::Full: break;
4438 case CCValAssign::AExt:
4439 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4440 break;
4441 case CCValAssign::ZExt:
4442 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4443 break;
4444 case CCValAssign::SExt:
4445 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4446 break;
4447 }
4448
4449 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4450 Flag = Chain.getValue(1);
4451 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4452 }
4453
4454 RetOps[0] = Chain; // Update chain.
4455
4456 // Add the flag if we have it.
4457 if (Flag.getNode())
4458 RetOps.push_back(Flag);
4459
4460 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4461 &RetOps[0], RetOps.size());
4462 }
4463
LowerSTACKRESTORE(SDValue Op,SelectionDAG & DAG,const PPCSubtarget & Subtarget) const4464 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4465 const PPCSubtarget &Subtarget) const {
4466 // When we pop the dynamic allocation we need to restore the SP link.
4467 DebugLoc dl = Op.getDebugLoc();
4468
4469 // Get the corect type for pointers.
4470 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4471
4472 // Construct the stack pointer operand.
4473 bool isPPC64 = Subtarget.isPPC64();
4474 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4475 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4476
4477 // Get the operands for the STACKRESTORE.
4478 SDValue Chain = Op.getOperand(0);
4479 SDValue SaveSP = Op.getOperand(1);
4480
4481 // Load the old link SP.
4482 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4483 MachinePointerInfo(),
4484 false, false, false, 0);
4485
4486 // Restore the stack pointer.
4487 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4488
4489 // Store the old link SP.
4490 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4491 false, false, 0);
4492 }
4493
4494
4495
4496 SDValue
getReturnAddrFrameIndex(SelectionDAG & DAG) const4497 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4498 MachineFunction &MF = DAG.getMachineFunction();
4499 bool isPPC64 = PPCSubTarget.isPPC64();
4500 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4501 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4502
4503 // Get current frame pointer save index. The users of this index will be
4504 // primarily DYNALLOC instructions.
4505 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4506 int RASI = FI->getReturnAddrSaveIndex();
4507
4508 // If the frame pointer save index hasn't been defined yet.
4509 if (!RASI) {
4510 // Find out what the fix offset of the frame pointer save area.
4511 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4512 // Allocate the frame index for frame pointer save area.
4513 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4514 // Save the result.
4515 FI->setReturnAddrSaveIndex(RASI);
4516 }
4517 return DAG.getFrameIndex(RASI, PtrVT);
4518 }
4519
4520 SDValue
getFramePointerFrameIndex(SelectionDAG & DAG) const4521 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4522 MachineFunction &MF = DAG.getMachineFunction();
4523 bool isPPC64 = PPCSubTarget.isPPC64();
4524 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4525 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4526
4527 // Get current frame pointer save index. The users of this index will be
4528 // primarily DYNALLOC instructions.
4529 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4530 int FPSI = FI->getFramePointerSaveIndex();
4531
4532 // If the frame pointer save index hasn't been defined yet.
4533 if (!FPSI) {
4534 // Find out what the fix offset of the frame pointer save area.
4535 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4536 isDarwinABI);
4537
4538 // Allocate the frame index for frame pointer save area.
4539 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4540 // Save the result.
4541 FI->setFramePointerSaveIndex(FPSI);
4542 }
4543 return DAG.getFrameIndex(FPSI, PtrVT);
4544 }
4545
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const PPCSubtarget & Subtarget) const4546 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4547 SelectionDAG &DAG,
4548 const PPCSubtarget &Subtarget) const {
4549 // Get the inputs.
4550 SDValue Chain = Op.getOperand(0);
4551 SDValue Size = Op.getOperand(1);
4552 DebugLoc dl = Op.getDebugLoc();
4553
4554 // Get the corect type for pointers.
4555 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4556 // Negate the size.
4557 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4558 DAG.getConstant(0, PtrVT), Size);
4559 // Construct a node for the frame pointer save index.
4560 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4561 // Build a DYNALLOC node.
4562 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4563 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4564 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4565 }
4566
4567 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4568 /// possible.
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const4569 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4570 // Not FP? Not a fsel.
4571 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4572 !Op.getOperand(2).getValueType().isFloatingPoint())
4573 return Op;
4574
4575 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4576
4577 // Cannot handle SETEQ/SETNE.
4578 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
4579
4580 EVT ResVT = Op.getValueType();
4581 EVT CmpVT = Op.getOperand(0).getValueType();
4582 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4583 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4584 DebugLoc dl = Op.getDebugLoc();
4585
4586 // If the RHS of the comparison is a 0.0, we don't need to do the
4587 // subtraction at all.
4588 if (isFloatingPointZero(RHS))
4589 switch (CC) {
4590 default: break; // SETUO etc aren't handled by fsel.
4591 case ISD::SETULT:
4592 case ISD::SETLT:
4593 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4594 case ISD::SETOGE:
4595 case ISD::SETGE:
4596 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4597 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4598 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4599 case ISD::SETUGT:
4600 case ISD::SETGT:
4601 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4602 case ISD::SETOLE:
4603 case ISD::SETLE:
4604 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4605 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4606 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4607 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4608 }
4609
4610 SDValue Cmp;
4611 switch (CC) {
4612 default: break; // SETUO etc aren't handled by fsel.
4613 case ISD::SETULT:
4614 case ISD::SETLT:
4615 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4616 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4617 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4618 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4619 case ISD::SETOGE:
4620 case ISD::SETGE:
4621 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4622 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4623 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4624 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4625 case ISD::SETUGT:
4626 case ISD::SETGT:
4627 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4628 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4629 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4630 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4631 case ISD::SETOLE:
4632 case ISD::SETLE:
4633 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4634 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4635 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4636 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4637 }
4638 return Op;
4639 }
4640
4641 // FIXME: Split this code up when LegalizeDAGTypes lands.
LowerFP_TO_INT(SDValue Op,SelectionDAG & DAG,DebugLoc dl) const4642 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4643 DebugLoc dl) const {
4644 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4645 SDValue Src = Op.getOperand(0);
4646 if (Src.getValueType() == MVT::f32)
4647 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4648
4649 SDValue Tmp;
4650 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4651 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4652 case MVT::i32:
4653 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4654 PPCISD::FCTIDZ,
4655 dl, MVT::f64, Src);
4656 break;
4657 case MVT::i64:
4658 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
4659 break;
4660 }
4661
4662 // Convert the FP value to an int value through memory.
4663 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
4664
4665 // Emit a store to the stack slot.
4666 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4667 MachinePointerInfo(), false, false, 0);
4668
4669 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4670 // add in a bias.
4671 if (Op.getValueType() == MVT::i32)
4672 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4673 DAG.getConstant(4, FIPtr.getValueType()));
4674 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
4675 false, false, false, 0);
4676 }
4677
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG) const4678 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
4679 SelectionDAG &DAG) const {
4680 DebugLoc dl = Op.getDebugLoc();
4681 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4682 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4683 return SDValue();
4684
4685 if (Op.getOperand(0).getValueType() == MVT::i64) {
4686 SDValue SINT = Op.getOperand(0);
4687 // When converting to single-precision, we actually need to convert
4688 // to double-precision first and then round to single-precision.
4689 // To avoid double-rounding effects during that operation, we have
4690 // to prepare the input operand. Bits that might be truncated when
4691 // converting to double-precision are replaced by a bit that won't
4692 // be lost at this stage, but is below the single-precision rounding
4693 // position.
4694 //
4695 // However, if -enable-unsafe-fp-math is in effect, accept double
4696 // rounding to avoid the extra overhead.
4697 if (Op.getValueType() == MVT::f32 &&
4698 !DAG.getTarget().Options.UnsafeFPMath) {
4699
4700 // Twiddle input to make sure the low 11 bits are zero. (If this
4701 // is the case, we are guaranteed the value will fit into the 53 bit
4702 // mantissa of an IEEE double-precision value without rounding.)
4703 // If any of those low 11 bits were not zero originally, make sure
4704 // bit 12 (value 2048) is set instead, so that the final rounding
4705 // to single-precision gets the correct result.
4706 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4707 SINT, DAG.getConstant(2047, MVT::i64));
4708 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4709 Round, DAG.getConstant(2047, MVT::i64));
4710 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4711 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4712 Round, DAG.getConstant(-2048, MVT::i64));
4713
4714 // However, we cannot use that value unconditionally: if the magnitude
4715 // of the input value is small, the bit-twiddling we did above might
4716 // end up visibly changing the output. Fortunately, in that case, we
4717 // don't need to twiddle bits since the original input will convert
4718 // exactly to double-precision floating-point already. Therefore,
4719 // construct a conditional to use the original value if the top 11
4720 // bits are all sign-bit copies, and use the rounded value computed
4721 // above otherwise.
4722 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4723 SINT, DAG.getConstant(53, MVT::i32));
4724 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4725 Cond, DAG.getConstant(1, MVT::i64));
4726 Cond = DAG.getSetCC(dl, MVT::i32,
4727 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4728
4729 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4730 }
4731 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4732 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
4733 if (Op.getValueType() == MVT::f32)
4734 FP = DAG.getNode(ISD::FP_ROUND, dl,
4735 MVT::f32, FP, DAG.getIntPtrConstant(0));
4736 return FP;
4737 }
4738
4739 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4740 "Unhandled SINT_TO_FP type in custom expander!");
4741 // Since we only generate this in 64-bit mode, we can take advantage of
4742 // 64-bit registers. In particular, sign extend the input value into the
4743 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4744 // then lfd it and fcfid it.
4745 MachineFunction &MF = DAG.getMachineFunction();
4746 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4747 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4748 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4749 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4750
4751 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
4752 Op.getOperand(0));
4753
4754 // STD the extended value into the stack slot.
4755 MachineMemOperand *MMO =
4756 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4757 MachineMemOperand::MOStore, 8, 8);
4758 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
4759 SDValue Store =
4760 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
4761 Ops, 4, MVT::i64, MMO);
4762 // Load the value as a double.
4763 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
4764 false, false, false, 0);
4765
4766 // FCFID it and return it.
4767 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
4768 if (Op.getValueType() == MVT::f32)
4769 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4770 return FP;
4771 }
4772
LowerFLT_ROUNDS_(SDValue Op,SelectionDAG & DAG) const4773 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4774 SelectionDAG &DAG) const {
4775 DebugLoc dl = Op.getDebugLoc();
4776 /*
4777 The rounding mode is in bits 30:31 of FPSR, and has the following
4778 settings:
4779 00 Round to nearest
4780 01 Round to 0
4781 10 Round to +inf
4782 11 Round to -inf
4783
4784 FLT_ROUNDS, on the other hand, expects the following:
4785 -1 Undefined
4786 0 Round to 0
4787 1 Round to nearest
4788 2 Round to +inf
4789 3 Round to -inf
4790
4791 To perform the conversion, we do:
4792 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4793 */
4794
4795 MachineFunction &MF = DAG.getMachineFunction();
4796 EVT VT = Op.getValueType();
4797 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4798 SDValue MFFSreg, InFlag;
4799
4800 // Save FP Control Word to register
4801 EVT NodeTys[] = {
4802 MVT::f64, // return register
4803 MVT::Glue // unused in this context
4804 };
4805 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4806
4807 // Save FP register to stack slot
4808 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4809 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4810 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4811 StackSlot, MachinePointerInfo(), false, false,0);
4812
4813 // Load FP Control Word from low 32 bits of stack slot.
4814 SDValue Four = DAG.getConstant(4, PtrVT);
4815 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4816 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4817 false, false, false, 0);
4818
4819 // Transform as necessary
4820 SDValue CWD1 =
4821 DAG.getNode(ISD::AND, dl, MVT::i32,
4822 CWD, DAG.getConstant(3, MVT::i32));
4823 SDValue CWD2 =
4824 DAG.getNode(ISD::SRL, dl, MVT::i32,
4825 DAG.getNode(ISD::AND, dl, MVT::i32,
4826 DAG.getNode(ISD::XOR, dl, MVT::i32,
4827 CWD, DAG.getConstant(3, MVT::i32)),
4828 DAG.getConstant(3, MVT::i32)),
4829 DAG.getConstant(1, MVT::i32));
4830
4831 SDValue RetVal =
4832 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4833
4834 return DAG.getNode((VT.getSizeInBits() < 16 ?
4835 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4836 }
4837
LowerSHL_PARTS(SDValue Op,SelectionDAG & DAG) const4838 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4839 EVT VT = Op.getValueType();
4840 unsigned BitWidth = VT.getSizeInBits();
4841 DebugLoc dl = Op.getDebugLoc();
4842 assert(Op.getNumOperands() == 3 &&
4843 VT == Op.getOperand(1).getValueType() &&
4844 "Unexpected SHL!");
4845
4846 // Expand into a bunch of logical ops. Note that these ops
4847 // depend on the PPC behavior for oversized shift amounts.
4848 SDValue Lo = Op.getOperand(0);
4849 SDValue Hi = Op.getOperand(1);
4850 SDValue Amt = Op.getOperand(2);
4851 EVT AmtVT = Amt.getValueType();
4852
4853 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4854 DAG.getConstant(BitWidth, AmtVT), Amt);
4855 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4856 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4857 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4858 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4859 DAG.getConstant(-BitWidth, AmtVT));
4860 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4861 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4862 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4863 SDValue OutOps[] = { OutLo, OutHi };
4864 return DAG.getMergeValues(OutOps, 2, dl);
4865 }
4866
LowerSRL_PARTS(SDValue Op,SelectionDAG & DAG) const4867 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4868 EVT VT = Op.getValueType();
4869 DebugLoc dl = Op.getDebugLoc();
4870 unsigned BitWidth = VT.getSizeInBits();
4871 assert(Op.getNumOperands() == 3 &&
4872 VT == Op.getOperand(1).getValueType() &&
4873 "Unexpected SRL!");
4874
4875 // Expand into a bunch of logical ops. Note that these ops
4876 // depend on the PPC behavior for oversized shift amounts.
4877 SDValue Lo = Op.getOperand(0);
4878 SDValue Hi = Op.getOperand(1);
4879 SDValue Amt = Op.getOperand(2);
4880 EVT AmtVT = Amt.getValueType();
4881
4882 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4883 DAG.getConstant(BitWidth, AmtVT), Amt);
4884 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4885 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4886 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4887 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4888 DAG.getConstant(-BitWidth, AmtVT));
4889 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4890 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4891 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4892 SDValue OutOps[] = { OutLo, OutHi };
4893 return DAG.getMergeValues(OutOps, 2, dl);
4894 }
4895
LowerSRA_PARTS(SDValue Op,SelectionDAG & DAG) const4896 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4897 DebugLoc dl = Op.getDebugLoc();
4898 EVT VT = Op.getValueType();
4899 unsigned BitWidth = VT.getSizeInBits();
4900 assert(Op.getNumOperands() == 3 &&
4901 VT == Op.getOperand(1).getValueType() &&
4902 "Unexpected SRA!");
4903
4904 // Expand into a bunch of logical ops, followed by a select_cc.
4905 SDValue Lo = Op.getOperand(0);
4906 SDValue Hi = Op.getOperand(1);
4907 SDValue Amt = Op.getOperand(2);
4908 EVT AmtVT = Amt.getValueType();
4909
4910 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4911 DAG.getConstant(BitWidth, AmtVT), Amt);
4912 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4913 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4914 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4915 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4916 DAG.getConstant(-BitWidth, AmtVT));
4917 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
4918 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
4919 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
4920 Tmp4, Tmp6, ISD::SETLE);
4921 SDValue OutOps[] = { OutLo, OutHi };
4922 return DAG.getMergeValues(OutOps, 2, dl);
4923 }
4924
4925 //===----------------------------------------------------------------------===//
4926 // Vector related lowering.
4927 //
4928
4929 /// BuildSplatI - Build a canonical splati of Val with an element size of
4930 /// SplatSize. Cast the result to VT.
BuildSplatI(int Val,unsigned SplatSize,EVT VT,SelectionDAG & DAG,DebugLoc dl)4931 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
4932 SelectionDAG &DAG, DebugLoc dl) {
4933 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
4934
4935 static const EVT VTys[] = { // canonical VT to use for each size.
4936 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
4937 };
4938
4939 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
4940
4941 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
4942 if (Val == -1)
4943 SplatSize = 1;
4944
4945 EVT CanonicalVT = VTys[SplatSize-1];
4946
4947 // Build a canonical splat for this value.
4948 SDValue Elt = DAG.getConstant(Val, MVT::i32);
4949 SmallVector<SDValue, 8> Ops;
4950 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
4951 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
4952 &Ops[0], Ops.size());
4953 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
4954 }
4955
4956 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
4957 /// specified intrinsic ID.
BuildIntrinsicOp(unsigned IID,SDValue LHS,SDValue RHS,SelectionDAG & DAG,DebugLoc dl,EVT DestVT=MVT::Other)4958 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
4959 SelectionDAG &DAG, DebugLoc dl,
4960 EVT DestVT = MVT::Other) {
4961 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
4962 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4963 DAG.getConstant(IID, MVT::i32), LHS, RHS);
4964 }
4965
4966 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
4967 /// specified intrinsic ID.
BuildIntrinsicOp(unsigned IID,SDValue Op0,SDValue Op1,SDValue Op2,SelectionDAG & DAG,DebugLoc dl,EVT DestVT=MVT::Other)4968 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
4969 SDValue Op2, SelectionDAG &DAG,
4970 DebugLoc dl, EVT DestVT = MVT::Other) {
4971 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
4972 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4973 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
4974 }
4975
4976
4977 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
4978 /// amount. The result has the specified value type.
BuildVSLDOI(SDValue LHS,SDValue RHS,unsigned Amt,EVT VT,SelectionDAG & DAG,DebugLoc dl)4979 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
4980 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4981 // Force LHS/RHS to be the right type.
4982 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
4983 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
4984
4985 int Ops[16];
4986 for (unsigned i = 0; i != 16; ++i)
4987 Ops[i] = i + Amt;
4988 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
4989 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4990 }
4991
4992 // If this is a case we can't handle, return null and let the default
4993 // expansion code take care of it. If we CAN select this case, and if it
4994 // selects to a single instruction, return Op. Otherwise, if we can codegen
4995 // this case more efficiently than a constant pool load, lower it to the
4996 // sequence of ops that should be used.
LowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG) const4997 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
4998 SelectionDAG &DAG) const {
4999 DebugLoc dl = Op.getDebugLoc();
5000 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5001 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5002
5003 // Check if this is a splat of a constant value.
5004 APInt APSplatBits, APSplatUndef;
5005 unsigned SplatBitSize;
5006 bool HasAnyUndefs;
5007 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5008 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5009 return SDValue();
5010
5011 unsigned SplatBits = APSplatBits.getZExtValue();
5012 unsigned SplatUndef = APSplatUndef.getZExtValue();
5013 unsigned SplatSize = SplatBitSize / 8;
5014
5015 // First, handle single instruction cases.
5016
5017 // All zeros?
5018 if (SplatBits == 0) {
5019 // Canonicalize all zero vectors to be v4i32.
5020 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5021 SDValue Z = DAG.getConstant(0, MVT::i32);
5022 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5023 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5024 }
5025 return Op;
5026 }
5027
5028 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5029 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5030 (32-SplatBitSize));
5031 if (SextVal >= -16 && SextVal <= 15)
5032 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5033
5034
5035 // Two instruction sequences.
5036
5037 // If this value is in the range [-32,30] and is even, use:
5038 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5039 // If this value is in the range [17,31] and is odd, use:
5040 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5041 // If this value is in the range [-31,-17] and is odd, use:
5042 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5043 // Note the last two are three-instruction sequences.
5044 if (SextVal >= -32 && SextVal <= 31) {
5045 // To avoid having these optimizations undone by constant folding,
5046 // we convert to a pseudo that will be expanded later into one of
5047 // the above forms.
5048 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5049 EVT VT = Op.getValueType();
5050 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5051 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5052 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5053 }
5054
5055 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5056 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5057 // for fneg/fabs.
5058 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5059 // Make -1 and vspltisw -1:
5060 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5061
5062 // Make the VSLW intrinsic, computing 0x8000_0000.
5063 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5064 OnesV, DAG, dl);
5065
5066 // xor by OnesV to invert it.
5067 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5068 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5069 }
5070
5071 // Check to see if this is a wide variety of vsplti*, binop self cases.
5072 static const signed char SplatCsts[] = {
5073 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5074 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5075 };
5076
5077 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5078 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5079 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5080 int i = SplatCsts[idx];
5081
5082 // Figure out what shift amount will be used by altivec if shifted by i in
5083 // this splat size.
5084 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5085
5086 // vsplti + shl self.
5087 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5088 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5089 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5090 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5091 Intrinsic::ppc_altivec_vslw
5092 };
5093 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5094 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5095 }
5096
5097 // vsplti + srl self.
5098 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5099 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5100 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5101 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5102 Intrinsic::ppc_altivec_vsrw
5103 };
5104 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5105 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5106 }
5107
5108 // vsplti + sra self.
5109 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5110 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5111 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5112 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5113 Intrinsic::ppc_altivec_vsraw
5114 };
5115 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5116 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5117 }
5118
5119 // vsplti + rol self.
5120 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5121 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5122 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5123 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5124 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5125 Intrinsic::ppc_altivec_vrlw
5126 };
5127 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5128 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5129 }
5130
5131 // t = vsplti c, result = vsldoi t, t, 1
5132 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5133 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5134 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5135 }
5136 // t = vsplti c, result = vsldoi t, t, 2
5137 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5138 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5139 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5140 }
5141 // t = vsplti c, result = vsldoi t, t, 3
5142 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5143 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5144 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5145 }
5146 }
5147
5148 return SDValue();
5149 }
5150
5151 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5152 /// the specified operations to build the shuffle.
GeneratePerfectShuffle(unsigned PFEntry,SDValue LHS,SDValue RHS,SelectionDAG & DAG,DebugLoc dl)5153 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5154 SDValue RHS, SelectionDAG &DAG,
5155 DebugLoc dl) {
5156 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5157 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5158 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5159
5160 enum {
5161 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5162 OP_VMRGHW,
5163 OP_VMRGLW,
5164 OP_VSPLTISW0,
5165 OP_VSPLTISW1,
5166 OP_VSPLTISW2,
5167 OP_VSPLTISW3,
5168 OP_VSLDOI4,
5169 OP_VSLDOI8,
5170 OP_VSLDOI12
5171 };
5172
5173 if (OpNum == OP_COPY) {
5174 if (LHSID == (1*9+2)*9+3) return LHS;
5175 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5176 return RHS;
5177 }
5178
5179 SDValue OpLHS, OpRHS;
5180 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5181 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5182
5183 int ShufIdxs[16];
5184 switch (OpNum) {
5185 default: llvm_unreachable("Unknown i32 permute!");
5186 case OP_VMRGHW:
5187 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5188 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5189 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5190 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5191 break;
5192 case OP_VMRGLW:
5193 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5194 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5195 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5196 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5197 break;
5198 case OP_VSPLTISW0:
5199 for (unsigned i = 0; i != 16; ++i)
5200 ShufIdxs[i] = (i&3)+0;
5201 break;
5202 case OP_VSPLTISW1:
5203 for (unsigned i = 0; i != 16; ++i)
5204 ShufIdxs[i] = (i&3)+4;
5205 break;
5206 case OP_VSPLTISW2:
5207 for (unsigned i = 0; i != 16; ++i)
5208 ShufIdxs[i] = (i&3)+8;
5209 break;
5210 case OP_VSPLTISW3:
5211 for (unsigned i = 0; i != 16; ++i)
5212 ShufIdxs[i] = (i&3)+12;
5213 break;
5214 case OP_VSLDOI4:
5215 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5216 case OP_VSLDOI8:
5217 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5218 case OP_VSLDOI12:
5219 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5220 }
5221 EVT VT = OpLHS.getValueType();
5222 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5223 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5224 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5225 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5226 }
5227
5228 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5229 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5230 /// return the code it can be lowered into. Worst case, it can always be
5231 /// lowered into a vperm.
LowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG) const5232 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5233 SelectionDAG &DAG) const {
5234 DebugLoc dl = Op.getDebugLoc();
5235 SDValue V1 = Op.getOperand(0);
5236 SDValue V2 = Op.getOperand(1);
5237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5238 EVT VT = Op.getValueType();
5239
5240 // Cases that are handled by instructions that take permute immediates
5241 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5242 // selected by the instruction selector.
5243 if (V2.getOpcode() == ISD::UNDEF) {
5244 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5245 PPC::isSplatShuffleMask(SVOp, 2) ||
5246 PPC::isSplatShuffleMask(SVOp, 4) ||
5247 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5248 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5249 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5250 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5251 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5252 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5253 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5254 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5255 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5256 return Op;
5257 }
5258 }
5259
5260 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5261 // and produce a fixed permutation. If any of these match, do not lower to
5262 // VPERM.
5263 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5264 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5265 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5266 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5267 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5268 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5269 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5270 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5271 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5272 return Op;
5273
5274 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5275 // perfect shuffle table to emit an optimal matching sequence.
5276 ArrayRef<int> PermMask = SVOp->getMask();
5277
5278 unsigned PFIndexes[4];
5279 bool isFourElementShuffle = true;
5280 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5281 unsigned EltNo = 8; // Start out undef.
5282 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5283 if (PermMask[i*4+j] < 0)
5284 continue; // Undef, ignore it.
5285
5286 unsigned ByteSource = PermMask[i*4+j];
5287 if ((ByteSource & 3) != j) {
5288 isFourElementShuffle = false;
5289 break;
5290 }
5291
5292 if (EltNo == 8) {
5293 EltNo = ByteSource/4;
5294 } else if (EltNo != ByteSource/4) {
5295 isFourElementShuffle = false;
5296 break;
5297 }
5298 }
5299 PFIndexes[i] = EltNo;
5300 }
5301
5302 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5303 // perfect shuffle vector to determine if it is cost effective to do this as
5304 // discrete instructions, or whether we should use a vperm.
5305 if (isFourElementShuffle) {
5306 // Compute the index in the perfect shuffle table.
5307 unsigned PFTableIndex =
5308 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5309
5310 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5311 unsigned Cost = (PFEntry >> 30);
5312
5313 // Determining when to avoid vperm is tricky. Many things affect the cost
5314 // of vperm, particularly how many times the perm mask needs to be computed.
5315 // For example, if the perm mask can be hoisted out of a loop or is already
5316 // used (perhaps because there are multiple permutes with the same shuffle
5317 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5318 // the loop requires an extra register.
5319 //
5320 // As a compromise, we only emit discrete instructions if the shuffle can be
5321 // generated in 3 or fewer operations. When we have loop information
5322 // available, if this block is within a loop, we should avoid using vperm
5323 // for 3-operation perms and use a constant pool load instead.
5324 if (Cost < 3)
5325 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5326 }
5327
5328 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5329 // vector that will get spilled to the constant pool.
5330 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5331
5332 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5333 // that it is in input element units, not in bytes. Convert now.
5334 EVT EltVT = V1.getValueType().getVectorElementType();
5335 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5336
5337 SmallVector<SDValue, 16> ResultMask;
5338 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5339 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5340
5341 for (unsigned j = 0; j != BytesPerElement; ++j)
5342 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5343 MVT::i32));
5344 }
5345
5346 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5347 &ResultMask[0], ResultMask.size());
5348 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5349 }
5350
5351 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5352 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5353 /// information about the intrinsic.
getAltivecCompareInfo(SDValue Intrin,int & CompareOpc,bool & isDot)5354 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5355 bool &isDot) {
5356 unsigned IntrinsicID =
5357 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5358 CompareOpc = -1;
5359 isDot = false;
5360 switch (IntrinsicID) {
5361 default: return false;
5362 // Comparison predicates.
5363 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5364 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5365 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5366 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5367 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5368 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5369 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5370 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5371 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5372 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5373 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5374 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5375 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5376
5377 // Normal Comparisons.
5378 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5379 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5380 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5381 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5382 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5383 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5384 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5385 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5386 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5387 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5388 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5389 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5390 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5391 }
5392 return true;
5393 }
5394
5395 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5396 /// lower, do it, otherwise return null.
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const5397 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5398 SelectionDAG &DAG) const {
5399 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5400 // opcode number of the comparison.
5401 DebugLoc dl = Op.getDebugLoc();
5402 int CompareOpc;
5403 bool isDot;
5404 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5405 return SDValue(); // Don't custom lower most intrinsics.
5406
5407 // If this is a non-dot comparison, make the VCMP node and we are done.
5408 if (!isDot) {
5409 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5410 Op.getOperand(1), Op.getOperand(2),
5411 DAG.getConstant(CompareOpc, MVT::i32));
5412 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5413 }
5414
5415 // Create the PPCISD altivec 'dot' comparison node.
5416 SDValue Ops[] = {
5417 Op.getOperand(2), // LHS
5418 Op.getOperand(3), // RHS
5419 DAG.getConstant(CompareOpc, MVT::i32)
5420 };
5421 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5422 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5423
5424 // Now that we have the comparison, emit a copy from the CR to a GPR.
5425 // This is flagged to the above dot comparison.
5426 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5427 DAG.getRegister(PPC::CR6, MVT::i32),
5428 CompNode.getValue(1));
5429
5430 // Unpack the result based on how the target uses it.
5431 unsigned BitNo; // Bit # of CR6.
5432 bool InvertBit; // Invert result?
5433 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5434 default: // Can't happen, don't crash on invalid number though.
5435 case 0: // Return the value of the EQ bit of CR6.
5436 BitNo = 0; InvertBit = false;
5437 break;
5438 case 1: // Return the inverted value of the EQ bit of CR6.
5439 BitNo = 0; InvertBit = true;
5440 break;
5441 case 2: // Return the value of the LT bit of CR6.
5442 BitNo = 2; InvertBit = false;
5443 break;
5444 case 3: // Return the inverted value of the LT bit of CR6.
5445 BitNo = 2; InvertBit = true;
5446 break;
5447 }
5448
5449 // Shift the bit into the low position.
5450 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5451 DAG.getConstant(8-(3-BitNo), MVT::i32));
5452 // Isolate the bit.
5453 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5454 DAG.getConstant(1, MVT::i32));
5455
5456 // If we are supposed to, toggle the bit.
5457 if (InvertBit)
5458 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5459 DAG.getConstant(1, MVT::i32));
5460 return Flags;
5461 }
5462
LowerSCALAR_TO_VECTOR(SDValue Op,SelectionDAG & DAG) const5463 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5464 SelectionDAG &DAG) const {
5465 DebugLoc dl = Op.getDebugLoc();
5466 // Create a stack slot that is 16-byte aligned.
5467 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5468 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5469 EVT PtrVT = getPointerTy();
5470 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5471
5472 // Store the input value into Value#0 of the stack slot.
5473 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5474 Op.getOperand(0), FIdx, MachinePointerInfo(),
5475 false, false, 0);
5476 // Load it out.
5477 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5478 false, false, false, 0);
5479 }
5480
LowerMUL(SDValue Op,SelectionDAG & DAG) const5481 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5482 DebugLoc dl = Op.getDebugLoc();
5483 if (Op.getValueType() == MVT::v4i32) {
5484 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5485
5486 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5487 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5488
5489 SDValue RHSSwap = // = vrlw RHS, 16
5490 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5491
5492 // Shrinkify inputs to v8i16.
5493 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5494 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5495 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5496
5497 // Low parts multiplied together, generating 32-bit results (we ignore the
5498 // top parts).
5499 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5500 LHS, RHS, DAG, dl, MVT::v4i32);
5501
5502 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5503 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5504 // Shift the high parts up 16 bits.
5505 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5506 Neg16, DAG, dl);
5507 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5508 } else if (Op.getValueType() == MVT::v8i16) {
5509 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5510
5511 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5512
5513 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5514 LHS, RHS, Zero, DAG, dl);
5515 } else if (Op.getValueType() == MVT::v16i8) {
5516 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5517
5518 // Multiply the even 8-bit parts, producing 16-bit sums.
5519 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5520 LHS, RHS, DAG, dl, MVT::v8i16);
5521 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5522
5523 // Multiply the odd 8-bit parts, producing 16-bit sums.
5524 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5525 LHS, RHS, DAG, dl, MVT::v8i16);
5526 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5527
5528 // Merge the results together.
5529 int Ops[16];
5530 for (unsigned i = 0; i != 8; ++i) {
5531 Ops[i*2 ] = 2*i+1;
5532 Ops[i*2+1] = 2*i+1+16;
5533 }
5534 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5535 } else {
5536 llvm_unreachable("Unknown mul to lower!");
5537 }
5538 }
5539
5540 /// LowerOperation - Provide custom lowering hooks for some operations.
5541 ///
LowerOperation(SDValue Op,SelectionDAG & DAG) const5542 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5543 switch (Op.getOpcode()) {
5544 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5545 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5546 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5547 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5548 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5549 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5550 case ISD::SETCC: return LowerSETCC(Op, DAG);
5551 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5552 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5553 case ISD::VASTART:
5554 return LowerVASTART(Op, DAG, PPCSubTarget);
5555
5556 case ISD::VAARG:
5557 return LowerVAARG(Op, DAG, PPCSubTarget);
5558
5559 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5560 case ISD::DYNAMIC_STACKALLOC:
5561 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5562
5563 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5564 case ISD::FP_TO_UINT:
5565 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5566 Op.getDebugLoc());
5567 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5568 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5569
5570 // Lower 64-bit shifts.
5571 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5572 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5573 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5574
5575 // Vector-related lowering.
5576 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5577 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5578 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5579 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5580 case ISD::MUL: return LowerMUL(Op, DAG);
5581
5582 // Frame & Return address.
5583 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5584 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5585 }
5586 }
5587
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const5588 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5589 SmallVectorImpl<SDValue>&Results,
5590 SelectionDAG &DAG) const {
5591 const TargetMachine &TM = getTargetMachine();
5592 DebugLoc dl = N->getDebugLoc();
5593 switch (N->getOpcode()) {
5594 default:
5595 llvm_unreachable("Do not know how to custom type legalize this operation!");
5596 case ISD::VAARG: {
5597 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5598 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5599 return;
5600
5601 EVT VT = N->getValueType(0);
5602
5603 if (VT == MVT::i64) {
5604 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5605
5606 Results.push_back(NewNode);
5607 Results.push_back(NewNode.getValue(1));
5608 }
5609 return;
5610 }
5611 case ISD::FP_ROUND_INREG: {
5612 assert(N->getValueType(0) == MVT::ppcf128);
5613 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5614 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5615 MVT::f64, N->getOperand(0),
5616 DAG.getIntPtrConstant(0));
5617 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5618 MVT::f64, N->getOperand(0),
5619 DAG.getIntPtrConstant(1));
5620
5621 // This sequence changes FPSCR to do round-to-zero, adds the two halves
5622 // of the long double, and puts FPSCR back the way it was. We do not
5623 // actually model FPSCR.
5624 std::vector<EVT> NodeTys;
5625 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
5626
5627 NodeTys.push_back(MVT::f64); // Return register
5628 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
5629 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5630 MFFSreg = Result.getValue(0);
5631 InFlag = Result.getValue(1);
5632
5633 NodeTys.clear();
5634 NodeTys.push_back(MVT::Glue); // Returns a flag
5635 Ops[0] = DAG.getConstant(31, MVT::i32);
5636 Ops[1] = InFlag;
5637 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
5638 InFlag = Result.getValue(0);
5639
5640 NodeTys.clear();
5641 NodeTys.push_back(MVT::Glue); // Returns a flag
5642 Ops[0] = DAG.getConstant(30, MVT::i32);
5643 Ops[1] = InFlag;
5644 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
5645 InFlag = Result.getValue(0);
5646
5647 NodeTys.clear();
5648 NodeTys.push_back(MVT::f64); // result of add
5649 NodeTys.push_back(MVT::Glue); // Returns a flag
5650 Ops[0] = Lo;
5651 Ops[1] = Hi;
5652 Ops[2] = InFlag;
5653 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
5654 FPreg = Result.getValue(0);
5655 InFlag = Result.getValue(1);
5656
5657 NodeTys.clear();
5658 NodeTys.push_back(MVT::f64);
5659 Ops[0] = DAG.getConstant(1, MVT::i32);
5660 Ops[1] = MFFSreg;
5661 Ops[2] = FPreg;
5662 Ops[3] = InFlag;
5663 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
5664 FPreg = Result.getValue(0);
5665
5666 // We know the low half is about to be thrown away, so just use something
5667 // convenient.
5668 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5669 FPreg, FPreg));
5670 return;
5671 }
5672 case ISD::FP_TO_SINT:
5673 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5674 return;
5675 }
5676 }
5677
5678
5679 //===----------------------------------------------------------------------===//
5680 // Other Lowering Code
5681 //===----------------------------------------------------------------------===//
5682
5683 MachineBasicBlock *
EmitAtomicBinary(MachineInstr * MI,MachineBasicBlock * BB,bool is64bit,unsigned BinOpcode) const5684 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5685 bool is64bit, unsigned BinOpcode) const {
5686 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5688
5689 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5690 MachineFunction *F = BB->getParent();
5691 MachineFunction::iterator It = BB;
5692 ++It;
5693
5694 unsigned dest = MI->getOperand(0).getReg();
5695 unsigned ptrA = MI->getOperand(1).getReg();
5696 unsigned ptrB = MI->getOperand(2).getReg();
5697 unsigned incr = MI->getOperand(3).getReg();
5698 DebugLoc dl = MI->getDebugLoc();
5699
5700 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5701 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5702 F->insert(It, loopMBB);
5703 F->insert(It, exitMBB);
5704 exitMBB->splice(exitMBB->begin(), BB,
5705 llvm::next(MachineBasicBlock::iterator(MI)),
5706 BB->end());
5707 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5708
5709 MachineRegisterInfo &RegInfo = F->getRegInfo();
5710 unsigned TmpReg = (!BinOpcode) ? incr :
5711 RegInfo.createVirtualRegister(
5712 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5713 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5714
5715 // thisMBB:
5716 // ...
5717 // fallthrough --> loopMBB
5718 BB->addSuccessor(loopMBB);
5719
5720 // loopMBB:
5721 // l[wd]arx dest, ptr
5722 // add r0, dest, incr
5723 // st[wd]cx. r0, ptr
5724 // bne- loopMBB
5725 // fallthrough --> exitMBB
5726 BB = loopMBB;
5727 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5728 .addReg(ptrA).addReg(ptrB);
5729 if (BinOpcode)
5730 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5731 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5732 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5733 BuildMI(BB, dl, TII->get(PPC::BCC))
5734 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5735 BB->addSuccessor(loopMBB);
5736 BB->addSuccessor(exitMBB);
5737
5738 // exitMBB:
5739 // ...
5740 BB = exitMBB;
5741 return BB;
5742 }
5743
5744 MachineBasicBlock *
EmitPartwordAtomicBinary(MachineInstr * MI,MachineBasicBlock * BB,bool is8bit,unsigned BinOpcode) const5745 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5746 MachineBasicBlock *BB,
5747 bool is8bit, // operation
5748 unsigned BinOpcode) const {
5749 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5750 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5751 // In 64 bit mode we have to use 64 bits for addresses, even though the
5752 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5753 // registers without caring whether they're 32 or 64, but here we're
5754 // doing actual arithmetic on the addresses.
5755 bool is64bit = PPCSubTarget.isPPC64();
5756 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5757
5758 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5759 MachineFunction *F = BB->getParent();
5760 MachineFunction::iterator It = BB;
5761 ++It;
5762
5763 unsigned dest = MI->getOperand(0).getReg();
5764 unsigned ptrA = MI->getOperand(1).getReg();
5765 unsigned ptrB = MI->getOperand(2).getReg();
5766 unsigned incr = MI->getOperand(3).getReg();
5767 DebugLoc dl = MI->getDebugLoc();
5768
5769 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5770 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5771 F->insert(It, loopMBB);
5772 F->insert(It, exitMBB);
5773 exitMBB->splice(exitMBB->begin(), BB,
5774 llvm::next(MachineBasicBlock::iterator(MI)),
5775 BB->end());
5776 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5777
5778 MachineRegisterInfo &RegInfo = F->getRegInfo();
5779 const TargetRegisterClass *RC =
5780 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5781 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5782 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5783 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5784 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5785 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5786 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5787 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5788 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5789 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5790 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5791 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5792 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5793 unsigned Ptr1Reg;
5794 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5795
5796 // thisMBB:
5797 // ...
5798 // fallthrough --> loopMBB
5799 BB->addSuccessor(loopMBB);
5800
5801 // The 4-byte load must be aligned, while a char or short may be
5802 // anywhere in the word. Hence all this nasty bookkeeping code.
5803 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5804 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5805 // xori shift, shift1, 24 [16]
5806 // rlwinm ptr, ptr1, 0, 0, 29
5807 // slw incr2, incr, shift
5808 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5809 // slw mask, mask2, shift
5810 // loopMBB:
5811 // lwarx tmpDest, ptr
5812 // add tmp, tmpDest, incr2
5813 // andc tmp2, tmpDest, mask
5814 // and tmp3, tmp, mask
5815 // or tmp4, tmp3, tmp2
5816 // stwcx. tmp4, ptr
5817 // bne- loopMBB
5818 // fallthrough --> exitMBB
5819 // srw dest, tmpDest, shift
5820 if (ptrA != ZeroReg) {
5821 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5822 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5823 .addReg(ptrA).addReg(ptrB);
5824 } else {
5825 Ptr1Reg = ptrB;
5826 }
5827 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5828 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5829 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5830 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5831 if (is64bit)
5832 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5833 .addReg(Ptr1Reg).addImm(0).addImm(61);
5834 else
5835 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5836 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5837 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5838 .addReg(incr).addReg(ShiftReg);
5839 if (is8bit)
5840 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5841 else {
5842 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5843 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5844 }
5845 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5846 .addReg(Mask2Reg).addReg(ShiftReg);
5847
5848 BB = loopMBB;
5849 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5850 .addReg(ZeroReg).addReg(PtrReg);
5851 if (BinOpcode)
5852 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5853 .addReg(Incr2Reg).addReg(TmpDestReg);
5854 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5855 .addReg(TmpDestReg).addReg(MaskReg);
5856 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5857 .addReg(TmpReg).addReg(MaskReg);
5858 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5859 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5860 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5861 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5862 BuildMI(BB, dl, TII->get(PPC::BCC))
5863 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5864 BB->addSuccessor(loopMBB);
5865 BB->addSuccessor(exitMBB);
5866
5867 // exitMBB:
5868 // ...
5869 BB = exitMBB;
5870 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5871 .addReg(ShiftReg);
5872 return BB;
5873 }
5874
5875 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const5876 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5877 MachineBasicBlock *BB) const {
5878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5879
5880 // To "insert" these instructions we actually have to insert their
5881 // control-flow patterns.
5882 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5883 MachineFunction::iterator It = BB;
5884 ++It;
5885
5886 MachineFunction *F = BB->getParent();
5887
5888 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
5889 MI->getOpcode() == PPC::SELECT_CC_I8)) {
5890 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
5891 PPC::ISEL8 : PPC::ISEL;
5892 unsigned SelectPred = MI->getOperand(4).getImm();
5893 DebugLoc dl = MI->getDebugLoc();
5894
5895 // The SelectPred is ((BI << 5) | BO) for a BCC
5896 unsigned BO = SelectPred & 0xF;
5897 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel");
5898
5899 unsigned TrueOpNo, FalseOpNo;
5900 if (BO == 12) {
5901 TrueOpNo = 2;
5902 FalseOpNo = 3;
5903 } else {
5904 TrueOpNo = 3;
5905 FalseOpNo = 2;
5906 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred);
5907 }
5908
5909 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
5910 .addReg(MI->getOperand(TrueOpNo).getReg())
5911 .addReg(MI->getOperand(FalseOpNo).getReg())
5912 .addImm(SelectPred).addReg(MI->getOperand(1).getReg());
5913 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
5914 MI->getOpcode() == PPC::SELECT_CC_I8 ||
5915 MI->getOpcode() == PPC::SELECT_CC_F4 ||
5916 MI->getOpcode() == PPC::SELECT_CC_F8 ||
5917 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
5918
5919
5920 // The incoming instruction knows the destination vreg to set, the
5921 // condition code register to branch on, the true/false values to
5922 // select between, and a branch opcode to use.
5923
5924 // thisMBB:
5925 // ...
5926 // TrueVal = ...
5927 // cmpTY ccX, r1, r2
5928 // bCC copy1MBB
5929 // fallthrough --> copy0MBB
5930 MachineBasicBlock *thisMBB = BB;
5931 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5932 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5933 unsigned SelectPred = MI->getOperand(4).getImm();
5934 DebugLoc dl = MI->getDebugLoc();
5935 F->insert(It, copy0MBB);
5936 F->insert(It, sinkMBB);
5937
5938 // Transfer the remainder of BB and its successor edges to sinkMBB.
5939 sinkMBB->splice(sinkMBB->begin(), BB,
5940 llvm::next(MachineBasicBlock::iterator(MI)),
5941 BB->end());
5942 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5943
5944 // Next, add the true and fallthrough blocks as its successors.
5945 BB->addSuccessor(copy0MBB);
5946 BB->addSuccessor(sinkMBB);
5947
5948 BuildMI(BB, dl, TII->get(PPC::BCC))
5949 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
5950
5951 // copy0MBB:
5952 // %FalseValue = ...
5953 // # fallthrough to sinkMBB
5954 BB = copy0MBB;
5955
5956 // Update machine-CFG edges
5957 BB->addSuccessor(sinkMBB);
5958
5959 // sinkMBB:
5960 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5961 // ...
5962 BB = sinkMBB;
5963 BuildMI(*BB, BB->begin(), dl,
5964 TII->get(PPC::PHI), MI->getOperand(0).getReg())
5965 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
5966 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5967 }
5968 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
5969 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
5970 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
5971 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
5972 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
5973 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
5974 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
5975 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
5976
5977 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
5978 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
5979 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
5980 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
5981 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
5982 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
5983 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
5984 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
5985
5986 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
5987 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
5988 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
5989 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
5990 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
5991 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
5992 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
5993 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
5994
5995 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
5996 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
5997 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
5998 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
5999 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6000 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6001 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6002 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6003
6004 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6005 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6006 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6007 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6008 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6009 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6010 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6011 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6012
6013 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6014 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6015 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6016 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6017 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6018 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6019 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6020 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6021
6022 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6023 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6024 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6025 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6026 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6027 BB = EmitAtomicBinary(MI, BB, false, 0);
6028 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6029 BB = EmitAtomicBinary(MI, BB, true, 0);
6030
6031 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6032 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6033 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6034
6035 unsigned dest = MI->getOperand(0).getReg();
6036 unsigned ptrA = MI->getOperand(1).getReg();
6037 unsigned ptrB = MI->getOperand(2).getReg();
6038 unsigned oldval = MI->getOperand(3).getReg();
6039 unsigned newval = MI->getOperand(4).getReg();
6040 DebugLoc dl = MI->getDebugLoc();
6041
6042 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6043 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6044 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6045 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6046 F->insert(It, loop1MBB);
6047 F->insert(It, loop2MBB);
6048 F->insert(It, midMBB);
6049 F->insert(It, exitMBB);
6050 exitMBB->splice(exitMBB->begin(), BB,
6051 llvm::next(MachineBasicBlock::iterator(MI)),
6052 BB->end());
6053 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6054
6055 // thisMBB:
6056 // ...
6057 // fallthrough --> loopMBB
6058 BB->addSuccessor(loop1MBB);
6059
6060 // loop1MBB:
6061 // l[wd]arx dest, ptr
6062 // cmp[wd] dest, oldval
6063 // bne- midMBB
6064 // loop2MBB:
6065 // st[wd]cx. newval, ptr
6066 // bne- loopMBB
6067 // b exitBB
6068 // midMBB:
6069 // st[wd]cx. dest, ptr
6070 // exitBB:
6071 BB = loop1MBB;
6072 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6073 .addReg(ptrA).addReg(ptrB);
6074 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6075 .addReg(oldval).addReg(dest);
6076 BuildMI(BB, dl, TII->get(PPC::BCC))
6077 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6078 BB->addSuccessor(loop2MBB);
6079 BB->addSuccessor(midMBB);
6080
6081 BB = loop2MBB;
6082 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6083 .addReg(newval).addReg(ptrA).addReg(ptrB);
6084 BuildMI(BB, dl, TII->get(PPC::BCC))
6085 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6086 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6087 BB->addSuccessor(loop1MBB);
6088 BB->addSuccessor(exitMBB);
6089
6090 BB = midMBB;
6091 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6092 .addReg(dest).addReg(ptrA).addReg(ptrB);
6093 BB->addSuccessor(exitMBB);
6094
6095 // exitMBB:
6096 // ...
6097 BB = exitMBB;
6098 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6099 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6100 // We must use 64-bit registers for addresses when targeting 64-bit,
6101 // since we're actually doing arithmetic on them. Other registers
6102 // can be 32-bit.
6103 bool is64bit = PPCSubTarget.isPPC64();
6104 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6105
6106 unsigned dest = MI->getOperand(0).getReg();
6107 unsigned ptrA = MI->getOperand(1).getReg();
6108 unsigned ptrB = MI->getOperand(2).getReg();
6109 unsigned oldval = MI->getOperand(3).getReg();
6110 unsigned newval = MI->getOperand(4).getReg();
6111 DebugLoc dl = MI->getDebugLoc();
6112
6113 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6114 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6115 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6116 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6117 F->insert(It, loop1MBB);
6118 F->insert(It, loop2MBB);
6119 F->insert(It, midMBB);
6120 F->insert(It, exitMBB);
6121 exitMBB->splice(exitMBB->begin(), BB,
6122 llvm::next(MachineBasicBlock::iterator(MI)),
6123 BB->end());
6124 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6125
6126 MachineRegisterInfo &RegInfo = F->getRegInfo();
6127 const TargetRegisterClass *RC =
6128 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6129 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6130 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6131 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6132 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6133 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6134 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6135 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6136 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6137 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6138 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6139 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6140 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6141 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6142 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6143 unsigned Ptr1Reg;
6144 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6145 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
6146 // thisMBB:
6147 // ...
6148 // fallthrough --> loopMBB
6149 BB->addSuccessor(loop1MBB);
6150
6151 // The 4-byte load must be aligned, while a char or short may be
6152 // anywhere in the word. Hence all this nasty bookkeeping code.
6153 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6154 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6155 // xori shift, shift1, 24 [16]
6156 // rlwinm ptr, ptr1, 0, 0, 29
6157 // slw newval2, newval, shift
6158 // slw oldval2, oldval,shift
6159 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6160 // slw mask, mask2, shift
6161 // and newval3, newval2, mask
6162 // and oldval3, oldval2, mask
6163 // loop1MBB:
6164 // lwarx tmpDest, ptr
6165 // and tmp, tmpDest, mask
6166 // cmpw tmp, oldval3
6167 // bne- midMBB
6168 // loop2MBB:
6169 // andc tmp2, tmpDest, mask
6170 // or tmp4, tmp2, newval3
6171 // stwcx. tmp4, ptr
6172 // bne- loop1MBB
6173 // b exitBB
6174 // midMBB:
6175 // stwcx. tmpDest, ptr
6176 // exitBB:
6177 // srw dest, tmpDest, shift
6178 if (ptrA != ZeroReg) {
6179 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6180 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6181 .addReg(ptrA).addReg(ptrB);
6182 } else {
6183 Ptr1Reg = ptrB;
6184 }
6185 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6186 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6187 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6188 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6189 if (is64bit)
6190 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6191 .addReg(Ptr1Reg).addImm(0).addImm(61);
6192 else
6193 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6194 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6195 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6196 .addReg(newval).addReg(ShiftReg);
6197 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6198 .addReg(oldval).addReg(ShiftReg);
6199 if (is8bit)
6200 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6201 else {
6202 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6203 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6204 .addReg(Mask3Reg).addImm(65535);
6205 }
6206 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6207 .addReg(Mask2Reg).addReg(ShiftReg);
6208 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6209 .addReg(NewVal2Reg).addReg(MaskReg);
6210 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6211 .addReg(OldVal2Reg).addReg(MaskReg);
6212
6213 BB = loop1MBB;
6214 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6215 .addReg(ZeroReg).addReg(PtrReg);
6216 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6217 .addReg(TmpDestReg).addReg(MaskReg);
6218 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6219 .addReg(TmpReg).addReg(OldVal3Reg);
6220 BuildMI(BB, dl, TII->get(PPC::BCC))
6221 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6222 BB->addSuccessor(loop2MBB);
6223 BB->addSuccessor(midMBB);
6224
6225 BB = loop2MBB;
6226 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6227 .addReg(TmpDestReg).addReg(MaskReg);
6228 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6229 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6230 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6231 .addReg(ZeroReg).addReg(PtrReg);
6232 BuildMI(BB, dl, TII->get(PPC::BCC))
6233 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6234 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6235 BB->addSuccessor(loop1MBB);
6236 BB->addSuccessor(exitMBB);
6237
6238 BB = midMBB;
6239 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6240 .addReg(ZeroReg).addReg(PtrReg);
6241 BB->addSuccessor(exitMBB);
6242
6243 // exitMBB:
6244 // ...
6245 BB = exitMBB;
6246 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6247 .addReg(ShiftReg);
6248 } else {
6249 llvm_unreachable("Unexpected instr type to insert");
6250 }
6251
6252 MI->eraseFromParent(); // The pseudo instruction is gone now.
6253 return BB;
6254 }
6255
6256 //===----------------------------------------------------------------------===//
6257 // Target Optimization Hooks
6258 //===----------------------------------------------------------------------===//
6259
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const6260 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6261 DAGCombinerInfo &DCI) const {
6262 const TargetMachine &TM = getTargetMachine();
6263 SelectionDAG &DAG = DCI.DAG;
6264 DebugLoc dl = N->getDebugLoc();
6265 switch (N->getOpcode()) {
6266 default: break;
6267 case PPCISD::SHL:
6268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6269 if (C->isNullValue()) // 0 << V -> 0.
6270 return N->getOperand(0);
6271 }
6272 break;
6273 case PPCISD::SRL:
6274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6275 if (C->isNullValue()) // 0 >>u V -> 0.
6276 return N->getOperand(0);
6277 }
6278 break;
6279 case PPCISD::SRA:
6280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6281 if (C->isNullValue() || // 0 >>s V -> 0.
6282 C->isAllOnesValue()) // -1 >>s V -> -1.
6283 return N->getOperand(0);
6284 }
6285 break;
6286
6287 case ISD::SINT_TO_FP:
6288 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6289 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6290 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6291 // We allow the src/dst to be either f32/f64, but the intermediate
6292 // type must be i64.
6293 if (N->getOperand(0).getValueType() == MVT::i64 &&
6294 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6295 SDValue Val = N->getOperand(0).getOperand(0);
6296 if (Val.getValueType() == MVT::f32) {
6297 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6298 DCI.AddToWorklist(Val.getNode());
6299 }
6300
6301 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6302 DCI.AddToWorklist(Val.getNode());
6303 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6304 DCI.AddToWorklist(Val.getNode());
6305 if (N->getValueType(0) == MVT::f32) {
6306 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6307 DAG.getIntPtrConstant(0));
6308 DCI.AddToWorklist(Val.getNode());
6309 }
6310 return Val;
6311 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6312 // If the intermediate type is i32, we can avoid the load/store here
6313 // too.
6314 }
6315 }
6316 }
6317 break;
6318 case ISD::STORE:
6319 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6320 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6321 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6322 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6323 N->getOperand(1).getValueType() == MVT::i32 &&
6324 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6325 SDValue Val = N->getOperand(1).getOperand(0);
6326 if (Val.getValueType() == MVT::f32) {
6327 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6328 DCI.AddToWorklist(Val.getNode());
6329 }
6330 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6331 DCI.AddToWorklist(Val.getNode());
6332
6333 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
6334 N->getOperand(2), N->getOperand(3));
6335 DCI.AddToWorklist(Val.getNode());
6336 return Val;
6337 }
6338
6339 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6340 if (cast<StoreSDNode>(N)->isUnindexed() &&
6341 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6342 N->getOperand(1).getNode()->hasOneUse() &&
6343 (N->getOperand(1).getValueType() == MVT::i32 ||
6344 N->getOperand(1).getValueType() == MVT::i16)) {
6345 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6346 // Do an any-extend to 32-bits if this is a half-word input.
6347 if (BSwapOp.getValueType() == MVT::i16)
6348 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6349
6350 SDValue Ops[] = {
6351 N->getOperand(0), BSwapOp, N->getOperand(2),
6352 DAG.getValueType(N->getOperand(1).getValueType())
6353 };
6354 return
6355 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6356 Ops, array_lengthof(Ops),
6357 cast<StoreSDNode>(N)->getMemoryVT(),
6358 cast<StoreSDNode>(N)->getMemOperand());
6359 }
6360 break;
6361 case ISD::BSWAP:
6362 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
6363 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6364 N->getOperand(0).hasOneUse() &&
6365 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
6366 SDValue Load = N->getOperand(0);
6367 LoadSDNode *LD = cast<LoadSDNode>(Load);
6368 // Create the byte-swapping load.
6369 SDValue Ops[] = {
6370 LD->getChain(), // Chain
6371 LD->getBasePtr(), // Ptr
6372 DAG.getValueType(N->getValueType(0)) // VT
6373 };
6374 SDValue BSLoad =
6375 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
6376 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
6377 LD->getMemoryVT(), LD->getMemOperand());
6378
6379 // If this is an i16 load, insert the truncate.
6380 SDValue ResVal = BSLoad;
6381 if (N->getValueType(0) == MVT::i16)
6382 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
6383
6384 // First, combine the bswap away. This makes the value produced by the
6385 // load dead.
6386 DCI.CombineTo(N, ResVal);
6387
6388 // Next, combine the load away, we give it a bogus result value but a real
6389 // chain result. The result value is dead because the bswap is dead.
6390 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6391
6392 // Return N so it doesn't get rechecked!
6393 return SDValue(N, 0);
6394 }
6395
6396 break;
6397 case PPCISD::VCMP: {
6398 // If a VCMPo node already exists with exactly the same operands as this
6399 // node, use its result instead of this node (VCMPo computes both a CR6 and
6400 // a normal output).
6401 //
6402 if (!N->getOperand(0).hasOneUse() &&
6403 !N->getOperand(1).hasOneUse() &&
6404 !N->getOperand(2).hasOneUse()) {
6405
6406 // Scan all of the users of the LHS, looking for VCMPo's that match.
6407 SDNode *VCMPoNode = 0;
6408
6409 SDNode *LHSN = N->getOperand(0).getNode();
6410 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
6411 UI != E; ++UI)
6412 if (UI->getOpcode() == PPCISD::VCMPo &&
6413 UI->getOperand(1) == N->getOperand(1) &&
6414 UI->getOperand(2) == N->getOperand(2) &&
6415 UI->getOperand(0) == N->getOperand(0)) {
6416 VCMPoNode = *UI;
6417 break;
6418 }
6419
6420 // If there is no VCMPo node, or if the flag value has a single use, don't
6421 // transform this.
6422 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
6423 break;
6424
6425 // Look at the (necessarily single) use of the flag value. If it has a
6426 // chain, this transformation is more complex. Note that multiple things
6427 // could use the value result, which we should ignore.
6428 SDNode *FlagUser = 0;
6429 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
6430 FlagUser == 0; ++UI) {
6431 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
6432 SDNode *User = *UI;
6433 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
6434 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
6435 FlagUser = User;
6436 break;
6437 }
6438 }
6439 }
6440
6441 // If the user is a MFCR instruction, we know this is safe. Otherwise we
6442 // give up for right now.
6443 if (FlagUser->getOpcode() == PPCISD::MFCR)
6444 return SDValue(VCMPoNode, 0);
6445 }
6446 break;
6447 }
6448 case ISD::BR_CC: {
6449 // If this is a branch on an altivec predicate comparison, lower this so
6450 // that we don't have to do a MFCR: instead, branch directly on CR6. This
6451 // lowering is done pre-legalize, because the legalizer lowers the predicate
6452 // compare down to code that is difficult to reassemble.
6453 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
6454 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
6455 int CompareOpc;
6456 bool isDot;
6457
6458 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
6459 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
6460 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
6461 assert(isDot && "Can't compare against a vector result!");
6462
6463 // If this is a comparison against something other than 0/1, then we know
6464 // that the condition is never/always true.
6465 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
6466 if (Val != 0 && Val != 1) {
6467 if (CC == ISD::SETEQ) // Cond never true, remove branch.
6468 return N->getOperand(0);
6469 // Always !=, turn it into an unconditional branch.
6470 return DAG.getNode(ISD::BR, dl, MVT::Other,
6471 N->getOperand(0), N->getOperand(4));
6472 }
6473
6474 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
6475
6476 // Create the PPCISD altivec 'dot' comparison node.
6477 SDValue Ops[] = {
6478 LHS.getOperand(2), // LHS of compare
6479 LHS.getOperand(3), // RHS of compare
6480 DAG.getConstant(CompareOpc, MVT::i32)
6481 };
6482 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
6483 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
6484
6485 // Unpack the result based on how the target uses it.
6486 PPC::Predicate CompOpc;
6487 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
6488 default: // Can't happen, don't crash on invalid number though.
6489 case 0: // Branch on the value of the EQ bit of CR6.
6490 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
6491 break;
6492 case 1: // Branch on the inverted value of the EQ bit of CR6.
6493 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
6494 break;
6495 case 2: // Branch on the value of the LT bit of CR6.
6496 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
6497 break;
6498 case 3: // Branch on the inverted value of the LT bit of CR6.
6499 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
6500 break;
6501 }
6502
6503 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
6504 DAG.getConstant(CompOpc, MVT::i32),
6505 DAG.getRegister(PPC::CR6, MVT::i32),
6506 N->getOperand(4), CompNode.getValue(1));
6507 }
6508 break;
6509 }
6510 }
6511
6512 return SDValue();
6513 }
6514
6515 //===----------------------------------------------------------------------===//
6516 // Inline Assembly Support
6517 //===----------------------------------------------------------------------===//
6518
computeMaskedBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const6519 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6520 APInt &KnownZero,
6521 APInt &KnownOne,
6522 const SelectionDAG &DAG,
6523 unsigned Depth) const {
6524 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
6525 switch (Op.getOpcode()) {
6526 default: break;
6527 case PPCISD::LBRX: {
6528 // lhbrx is known to have the top bits cleared out.
6529 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
6530 KnownZero = 0xFFFF0000;
6531 break;
6532 }
6533 case ISD::INTRINSIC_WO_CHAIN: {
6534 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
6535 default: break;
6536 case Intrinsic::ppc_altivec_vcmpbfp_p:
6537 case Intrinsic::ppc_altivec_vcmpeqfp_p:
6538 case Intrinsic::ppc_altivec_vcmpequb_p:
6539 case Intrinsic::ppc_altivec_vcmpequh_p:
6540 case Intrinsic::ppc_altivec_vcmpequw_p:
6541 case Intrinsic::ppc_altivec_vcmpgefp_p:
6542 case Intrinsic::ppc_altivec_vcmpgtfp_p:
6543 case Intrinsic::ppc_altivec_vcmpgtsb_p:
6544 case Intrinsic::ppc_altivec_vcmpgtsh_p:
6545 case Intrinsic::ppc_altivec_vcmpgtsw_p:
6546 case Intrinsic::ppc_altivec_vcmpgtub_p:
6547 case Intrinsic::ppc_altivec_vcmpgtuh_p:
6548 case Intrinsic::ppc_altivec_vcmpgtuw_p:
6549 KnownZero = ~1U; // All bits but the low one are known to be zero.
6550 break;
6551 }
6552 }
6553 }
6554 }
6555
6556
6557 /// getConstraintType - Given a constraint, return the type of
6558 /// constraint it is for this target.
6559 PPCTargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const6560 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6561 if (Constraint.size() == 1) {
6562 switch (Constraint[0]) {
6563 default: break;
6564 case 'b':
6565 case 'r':
6566 case 'f':
6567 case 'v':
6568 case 'y':
6569 return C_RegisterClass;
6570 case 'Z':
6571 // FIXME: While Z does indicate a memory constraint, it specifically
6572 // indicates an r+r address (used in conjunction with the 'y' modifier
6573 // in the replacement string). Currently, we're forcing the base
6574 // register to be r0 in the asm printer (which is interpreted as zero)
6575 // and forming the complete address in the second register. This is
6576 // suboptimal.
6577 return C_Memory;
6578 }
6579 }
6580 return TargetLowering::getConstraintType(Constraint);
6581 }
6582
6583 /// Examine constraint type and operand type and determine a weight value.
6584 /// This object must already have been set up with the operand type
6585 /// and the current alternative constraint selected.
6586 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const6587 PPCTargetLowering::getSingleConstraintMatchWeight(
6588 AsmOperandInfo &info, const char *constraint) const {
6589 ConstraintWeight weight = CW_Invalid;
6590 Value *CallOperandVal = info.CallOperandVal;
6591 // If we don't have a value, we can't do a match,
6592 // but allow it at the lowest weight.
6593 if (CallOperandVal == NULL)
6594 return CW_Default;
6595 Type *type = CallOperandVal->getType();
6596 // Look at the constraint type.
6597 switch (*constraint) {
6598 default:
6599 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6600 break;
6601 case 'b':
6602 if (type->isIntegerTy())
6603 weight = CW_Register;
6604 break;
6605 case 'f':
6606 if (type->isFloatTy())
6607 weight = CW_Register;
6608 break;
6609 case 'd':
6610 if (type->isDoubleTy())
6611 weight = CW_Register;
6612 break;
6613 case 'v':
6614 if (type->isVectorTy())
6615 weight = CW_Register;
6616 break;
6617 case 'y':
6618 weight = CW_Register;
6619 break;
6620 case 'Z':
6621 weight = CW_Memory;
6622 break;
6623 }
6624 return weight;
6625 }
6626
6627 std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string & Constraint,EVT VT) const6628 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6629 EVT VT) const {
6630 if (Constraint.size() == 1) {
6631 // GCC RS6000 Constraint Letters
6632 switch (Constraint[0]) {
6633 case 'b': // R1-R31
6634 case 'r': // R0-R31
6635 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6636 return std::make_pair(0U, &PPC::G8RCRegClass);
6637 return std::make_pair(0U, &PPC::GPRCRegClass);
6638 case 'f':
6639 if (VT == MVT::f32 || VT == MVT::i32)
6640 return std::make_pair(0U, &PPC::F4RCRegClass);
6641 if (VT == MVT::f64 || VT == MVT::i64)
6642 return std::make_pair(0U, &PPC::F8RCRegClass);
6643 break;
6644 case 'v':
6645 return std::make_pair(0U, &PPC::VRRCRegClass);
6646 case 'y': // crrc
6647 return std::make_pair(0U, &PPC::CRRCRegClass);
6648 }
6649 }
6650
6651 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6652 }
6653
6654
6655 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6656 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const6657 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6658 std::string &Constraint,
6659 std::vector<SDValue>&Ops,
6660 SelectionDAG &DAG) const {
6661 SDValue Result(0,0);
6662
6663 // Only support length 1 constraints.
6664 if (Constraint.length() > 1) return;
6665
6666 char Letter = Constraint[0];
6667 switch (Letter) {
6668 default: break;
6669 case 'I':
6670 case 'J':
6671 case 'K':
6672 case 'L':
6673 case 'M':
6674 case 'N':
6675 case 'O':
6676 case 'P': {
6677 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
6678 if (!CST) return; // Must be an immediate to match.
6679 unsigned Value = CST->getZExtValue();
6680 switch (Letter) {
6681 default: llvm_unreachable("Unknown constraint letter!");
6682 case 'I': // "I" is a signed 16-bit constant.
6683 if ((short)Value == (int)Value)
6684 Result = DAG.getTargetConstant(Value, Op.getValueType());
6685 break;
6686 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
6687 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
6688 if ((short)Value == 0)
6689 Result = DAG.getTargetConstant(Value, Op.getValueType());
6690 break;
6691 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
6692 if ((Value >> 16) == 0)
6693 Result = DAG.getTargetConstant(Value, Op.getValueType());
6694 break;
6695 case 'M': // "M" is a constant that is greater than 31.
6696 if (Value > 31)
6697 Result = DAG.getTargetConstant(Value, Op.getValueType());
6698 break;
6699 case 'N': // "N" is a positive constant that is an exact power of two.
6700 if ((int)Value > 0 && isPowerOf2_32(Value))
6701 Result = DAG.getTargetConstant(Value, Op.getValueType());
6702 break;
6703 case 'O': // "O" is the constant zero.
6704 if (Value == 0)
6705 Result = DAG.getTargetConstant(Value, Op.getValueType());
6706 break;
6707 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
6708 if ((short)-Value == (int)-Value)
6709 Result = DAG.getTargetConstant(Value, Op.getValueType());
6710 break;
6711 }
6712 break;
6713 }
6714 }
6715
6716 if (Result.getNode()) {
6717 Ops.push_back(Result);
6718 return;
6719 }
6720
6721 // Handle standard constraint letters.
6722 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6723 }
6724
6725 // isLegalAddressingMode - Return true if the addressing mode represented
6726 // by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode(const AddrMode & AM,Type * Ty) const6727 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6728 Type *Ty) const {
6729 // FIXME: PPC does not allow r+i addressing modes for vectors!
6730
6731 // PPC allows a sign-extended 16-bit immediate field.
6732 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
6733 return false;
6734
6735 // No global is ever allowed as a base.
6736 if (AM.BaseGV)
6737 return false;
6738
6739 // PPC only support r+r,
6740 switch (AM.Scale) {
6741 case 0: // "r+i" or just "i", depending on HasBaseReg.
6742 break;
6743 case 1:
6744 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
6745 return false;
6746 // Otherwise we have r+r or r+i.
6747 break;
6748 case 2:
6749 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
6750 return false;
6751 // Allow 2*r as r+r.
6752 break;
6753 default:
6754 // No other scales are supported.
6755 return false;
6756 }
6757
6758 return true;
6759 }
6760
6761 /// isLegalAddressImmediate - Return true if the integer value can be used
6762 /// as the offset of the target addressing mode for load / store of the
6763 /// given type.
isLegalAddressImmediate(int64_t V,Type * Ty) const6764 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
6765 // PPC allows a sign-extended 16-bit immediate field.
6766 return (V > -(1 << 16) && V < (1 << 16)-1);
6767 }
6768
isLegalAddressImmediate(GlobalValue * GV) const6769 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
6770 return false;
6771 }
6772
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const6773 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
6774 SelectionDAG &DAG) const {
6775 MachineFunction &MF = DAG.getMachineFunction();
6776 MachineFrameInfo *MFI = MF.getFrameInfo();
6777 MFI->setReturnAddressIsTaken(true);
6778
6779 DebugLoc dl = Op.getDebugLoc();
6780 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6781
6782 // Make sure the function does not optimize away the store of the RA to
6783 // the stack.
6784 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
6785 FuncInfo->setLRStoreRequired();
6786 bool isPPC64 = PPCSubTarget.isPPC64();
6787 bool isDarwinABI = PPCSubTarget.isDarwinABI();
6788
6789 if (Depth > 0) {
6790 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6791 SDValue Offset =
6792
6793 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
6794 isPPC64? MVT::i64 : MVT::i32);
6795 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6796 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6797 FrameAddr, Offset),
6798 MachinePointerInfo(), false, false, false, 0);
6799 }
6800
6801 // Just load the return address off the stack.
6802 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
6803 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6804 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
6805 }
6806
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const6807 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
6808 SelectionDAG &DAG) const {
6809 DebugLoc dl = Op.getDebugLoc();
6810 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6811
6812 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6813 bool isPPC64 = PtrVT == MVT::i64;
6814
6815 MachineFunction &MF = DAG.getMachineFunction();
6816 MachineFrameInfo *MFI = MF.getFrameInfo();
6817 MFI->setFrameAddressIsTaken(true);
6818 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
6819 MFI->hasVarSizedObjects()) &&
6820 MFI->getStackSize() &&
6821 !MF.getFunction()->getAttributes().
6822 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked);
6823 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
6824 (is31 ? PPC::R31 : PPC::R1);
6825 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
6826 PtrVT);
6827 while (Depth--)
6828 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
6829 FrameAddr, MachinePointerInfo(), false, false,
6830 false, 0);
6831 return FrameAddr;
6832 }
6833
6834 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const6835 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6836 // The PowerPC target isn't yet aware of offsets.
6837 return false;
6838 }
6839
6840 /// getOptimalMemOpType - Returns the target specific optimal type for load
6841 /// and store operations as a result of memset, memcpy, and memmove
6842 /// lowering. If DstAlign is zero that means it's safe to destination
6843 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
6844 /// means there isn't a need to check it against alignment requirement,
6845 /// probably because the source does not need to be loaded. If 'IsMemset' is
6846 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
6847 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
6848 /// source is constant so it does not need to be loaded.
6849 /// It returns EVT::Other if the type should be determined using generic
6850 /// target-independent logic.
getOptimalMemOpType(uint64_t Size,unsigned DstAlign,unsigned SrcAlign,bool IsMemset,bool ZeroMemset,bool MemcpyStrSrc,MachineFunction & MF) const6851 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
6852 unsigned DstAlign, unsigned SrcAlign,
6853 bool IsMemset, bool ZeroMemset,
6854 bool MemcpyStrSrc,
6855 MachineFunction &MF) const {
6856 if (this->PPCSubTarget.isPPC64()) {
6857 return MVT::i64;
6858 } else {
6859 return MVT::i32;
6860 }
6861 }
6862
allowsUnalignedMemoryAccesses(EVT VT,bool * Fast) const6863 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
6864 bool *Fast) const {
6865 if (DisablePPCUnaligned)
6866 return false;
6867
6868 // PowerPC supports unaligned memory access for simple non-vector types.
6869 // Although accessing unaligned addresses is not as efficient as accessing
6870 // aligned addresses, it is generally more efficient than manual expansion,
6871 // and generally only traps for software emulation when crossing page
6872 // boundaries.
6873
6874 if (!VT.isSimple())
6875 return false;
6876
6877 if (VT.getSimpleVT().isVector())
6878 return false;
6879
6880 if (VT == MVT::ppcf128)
6881 return false;
6882
6883 if (Fast)
6884 *Fast = true;
6885
6886 return true;
6887 }
6888
6889 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
6890 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
6891 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
6892 /// is expanded to mul + add.
isFMAFasterThanMulAndAdd(EVT VT) const6893 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
6894 if (!VT.isSimple())
6895 return false;
6896
6897 switch (VT.getSimpleVT().SimpleTy) {
6898 case MVT::f32:
6899 case MVT::f64:
6900 case MVT::v4f32:
6901 return true;
6902 default:
6903 break;
6904 }
6905
6906 return false;
6907 }
6908
getSchedulingPreference(SDNode * N) const6909 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
6910 if (DisableILPPref)
6911 return TargetLowering::getSchedulingPreference(N);
6912
6913 return Sched::ILP;
6914 }
6915
6916