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Searched refs:isReg (Results 1 – 25 of 143) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineOperand.h188 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
191 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
196 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
224 bool isReg() const { return OpKind == MO_Register; } in isReg() function
260 assert(isReg() && "This is not a register operand!"); in getReg()
265 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
270 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
275 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
280 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
285 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp117 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding()
139 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding()
150 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding()
161 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding()
173 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
195 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
216 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups); in getTLSRegEncoding()
241 if (MO.isReg()) { in getMachineOpValue()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp92 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
113 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
116 if (isReg() && isOnRegUseList()) in ChangeToImmediate()
139 bool WasReg = isReg(); in ChangeToRegister()
580 if (Operands[i].isReg()) in RemoveRegOperandsFromUseLists()
589 if (Operands[i].isReg()) in AddRegOperandsToUseLists()
642 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
686 if (NewMO->isReg()) { in addOperand()
721 if (Operands[i].isReg()) in RemoveOperand()
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DDeadMachineInstructionElim.cpp68 if (MO.isReg() && MO.isDef()) { in isDead()
125 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction()
154 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
173 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
DMachineLICM.cpp431 if (!MO.isReg()) in ProcessMI()
538 if (!MO.isReg()) in HoistRegionPostRA()
567 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
597 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
815 if (!MO.isReg() || MO.isImplicit()) in InitRegPressure()
847 if (!MO.isReg() || MO.isImplicit()) in UpdateRegPressure()
926 if (!MO.isReg()) in IsLoopInvariantInst()
976 if (!MO->isReg() || !MO->isDef()) in HasLoopPHIUse()
1023 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
1052 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
[all …]
DTargetInstrInfo.cpp122 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
133 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
192 if (!MI->getOperand(SrcOpIdx1).isReg() || in findCommutedOpIndices()
193 !MI->getOperand(SrcOpIdx2).isReg()) in findCommutedOpIndices()
227 if (MO.isReg()) { in PredicateInstruction()
442 if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) in isReallyTriviallyReMaterializableGeneric()
480 if (!MO.isReg()) continue; in isReallyTriviallyReMaterializableGeneric()
DExpandPostRAPseudos.cpp72 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
DMachineCSE.cpp119 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
169 if (!MO.isReg() || !MO.getReg()) in isPhysDefTriviallyDead()
201 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses()
220 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
296 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
383 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
519 if (!MO.isReg() || !MO.isDef()) in ProcessBlock()
DMachineInstrBundle.cpp54 if (MO.isReg() && MO.isInternalRead()) in runOnMachineFunction()
126 if (!MO.isReg()) in finalizeBundle()
257 if (!MO.isReg() || MO.getReg() != Reg) in analyzeVirtReg()
294 if (!MO.isReg()) in analyzePhysReg()
DRegisterScavenging.cpp145 if (!MO.isReg()) in forward()
170 if (!MO.isReg()) in forward()
279 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) in findSurvivorReg()
339 if (MO.isReg() && MO.getReg() != 0 && in scavengeRegister()
DMachineSink.cpp311 if (!MO.isReg()) continue; in isWorthBreakingCriticalEdge()
399 if (!MI->getOperand(0).isReg()) in collectDebugValues()
407 if (DI->getOperand(0).isReg() && in collectDebugValues()
485 if (!MO.isReg()) continue; // Ignore non-register operands. in FindSuccToSinkTo()
609 if (!MO.isReg()) continue; in SinkInstruction()
DTwoAddressInstructionPass.cpp188 if (!MO.isReg()) in sink3AddrInstruction()
261 if (!MO.isReg()) in sink3AddrInstruction()
434 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
798 if (!MO.isReg()) in rescheduleMIBelowKill()
841 if (!MO.isReg()) in rescheduleMIBelowKill()
984 if (!MO.isReg()) in rescheduleKillAboveMI()
1023 if (!MO.isReg()) in rescheduleKillAboveMI()
1231 if (MO.isReg() && in tryInstructionTransform()
1261 if (MOI->isReg()) in tryInstructionTransform()
1377 !MI->getOperand(i).isReg() || in processTiedPairs()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp252 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anon431341ec0111::CountValue
256 assert(isReg() && "Wrong CountValue accessor"); in getReg()
260 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
527 if (Op1.isReg()) { in getLoopTripCount()
570 if (InitialValue->isReg()) { in getLoopTripCount()
597 if (InitialValue->isReg()) { in getLoopTripCount()
604 if (EndValue->isReg()) { in getLoopTripCount()
630 if (Start->isReg()) { in computeCount()
635 if (End->isReg()) { in computeCount()
[all …]
DHexagonNewValueJump.cpp131 if (II->getOperand(i).isReg() && in canBeFeederToNewValueJump()
453 MI->getOperand(0).isReg() && in runOnMachineFunction()
461 isSecondOpReg = MI->getOperand(2).isReg(); in runOnMachineFunction()
495 if (MI->getOperand(0).isReg() && in runOnMachineFunction()
554 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
561 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
623 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
626 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
DHexagonAsmPrinter.cpp145 if (!MI->getOperand(OpNo).isReg() || in PrintAsmOperand()
147 !MI->getOperand(OpNo+1).isReg()) in PrintAsmOperand()
174 if (Base.isReg()) in PrintAsmMemoryOperand()
/external/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding()
200 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding()
209 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding()
219 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
235 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
257 if (MO.isReg()) { in getMachineOpValue()
DPPCCTRLoops.cpp154 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anon9f6c02960111::CountValue
159 assert(isReg() && "Wrong CountValue accessor"); in getReg()
177 if (isReg()) { OS << PrintReg(getReg()); } in print()
391 assert(InitialValue->isReg() && "Expecting register for init value"); in getTripCount()
464 MI->getOperand(1).isReg() && // could be a frame index instead in isInductionOperation()
481 if (MO.isReg() && MO.isDef() && in isInvalidLoopOperation()
516 if (MO.isReg() && MO.isDef()) { in isDead()
530 if (OPO.isReg() && OPO.isDef()) { in isDead()
573 if (!MO.isReg() || !MO.isDef()) in removeIfDead()
683 if (TripCount->isReg()) { in convertToCTRLoop()
/external/llvm/lib/CodeGen/AsmPrinter/
DAsmPrinterDwarf.cpp180 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove()
188 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove()
189 assert(Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove()
192 assert(!Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove()
/external/llvm/lib/Target/MBlaze/
DMBlazeDelaySlotFiller.cpp134 bool aop_is_reg = a->getOperand(aop).isReg(); in delayHasHazard()
142 bool mop_is_reg = m->getOperand(mop).isReg(); in delayHasHazard()
162 if (a->getOperand(aop).isReg()) { in delayHasHazard()
166 if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit()) { in delayHasHazard()
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp34 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg() in getDebugValueLocation()
47 if (!MO.isReg()) in printModifiedFPRAsmOperand()
70 } else if (MO.isReg()) { in printModifiedGPRAsmOperand()
269 assert(MO.isReg() && "unexpected inline assembly memory operand"); in PrintAsmMemoryOperand()
284 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); in PrintDebugValueComment()
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp76 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { in printOperand()
80 !MO.isReg() && !MO.isImm()) { in printOperand()
122 if (MI->getOperand(opNum+1).isReg() && in printMemOperand()
251 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && in getDebugValueLocation()
DDelaySlotFiller.cpp213 if (!MO.isReg()) in delayHasHazard()
244 assert(Reg.isReg() && "JMPL first operand is not a register."); in insertCallUses()
251 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register."); in insertCallUses()
265 if (!MO.isReg()) in insertDefsUses()
/external/llvm/include/llvm/MC/
DMCInst.h56 bool isReg() const { return Kind == kRegister; } in isReg() function
64 assert(isReg() && "This is not a register operand!"); in getReg()
70 assert(isReg() && "This is not a register operand!"); in setReg()
/external/llvm/lib/Target/R600/
DSIInsertWaits.cpp137 assert(Op.isReg() && "First LGKM operand must be a register!"); in getHwCounts()
153 if (!Op.isReg()) in isOpRelevant()
172 if (I->isReg() && I->isUse()) in isOpRelevant()
181 if (!Op.isReg()) in getRegInterval()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h115 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && in isLeaMem()
116 MI->getOperand(Op+2).isReg() && in isLeaMem()
126 MI->getOperand(Op+4).isReg() && in isMem()
345 if (!MO.isReg()) return false; in isX86_64ExtendedReg()

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