1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
16
17 #include "X86.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
24
25 namespace llvm {
26 class X86RegisterInfo;
27 class X86TargetMachine;
28
29 namespace X86 {
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
32 enum CondCode {
33 COND_A = 0,
34 COND_AE = 1,
35 COND_B = 2,
36 COND_BE = 3,
37 COND_E = 4,
38 COND_G = 5,
39 COND_GE = 6,
40 COND_L = 7,
41 COND_LE = 8,
42 COND_NE = 9,
43 COND_NO = 10,
44 COND_NP = 11,
45 COND_NS = 12,
46 COND_O = 13,
47 COND_P = 14,
48 COND_S = 15,
49
50 // Artificial condition codes. These are used by AnalyzeBranch
51 // to indicate a block terminated with two conditional branches to
52 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
53 // which can't be represented on x86 with a single condition. These
54 // are never used in MachineInstrs.
55 COND_NE_OR_P,
56 COND_NP_OR_E,
57
58 COND_INVALID
59 };
60
61 // Turn condition code into conditional branch opcode.
62 unsigned GetCondBranchFromCond(CondCode CC);
63
64 // Turn CMov opcode into condition code.
65 CondCode getCondFromCMovOpc(unsigned Opc);
66
67 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
68 /// e.g. turning COND_E to COND_NE.
69 CondCode GetOppositeBranchCondition(X86::CondCode CC);
70 } // end namespace X86;
71
72
73 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
74 /// a reference to a stub for a global, not the global itself.
isGlobalStubReference(unsigned char TargetFlag)75 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
76 switch (TargetFlag) {
77 case X86II::MO_DLLIMPORT: // dllimport stub.
78 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
79 case X86II::MO_GOT: // normal GOT reference.
80 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
81 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
82 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
83 return true;
84 default:
85 return false;
86 }
87 }
88
89 /// isGlobalRelativeToPICBase - Return true if the specified global value
90 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
91 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
isGlobalRelativeToPICBase(unsigned char TargetFlag)92 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
93 switch (TargetFlag) {
94 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
95 case X86II::MO_GOT: // isPICStyleGOT: other global.
96 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
97 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
98 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
99 case X86II::MO_TLVP: // ??? Pretty sure..
100 return true;
101 default:
102 return false;
103 }
104 }
105
isScale(const MachineOperand & MO)106 inline static bool isScale(const MachineOperand &MO) {
107 return MO.isImm() &&
108 (MO.getImm() == 1 || MO.getImm() == 2 ||
109 MO.getImm() == 4 || MO.getImm() == 8);
110 }
111
isLeaMem(const MachineInstr * MI,unsigned Op)112 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
113 if (MI->getOperand(Op).isFI()) return true;
114 return Op+4 <= MI->getNumOperands() &&
115 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
116 MI->getOperand(Op+2).isReg() &&
117 (MI->getOperand(Op+3).isImm() ||
118 MI->getOperand(Op+3).isGlobal() ||
119 MI->getOperand(Op+3).isCPI() ||
120 MI->getOperand(Op+3).isJTI());
121 }
122
isMem(const MachineInstr * MI,unsigned Op)123 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
124 if (MI->getOperand(Op).isFI()) return true;
125 return Op+5 <= MI->getNumOperands() &&
126 MI->getOperand(Op+4).isReg() &&
127 isLeaMem(MI, Op);
128 }
129
130 class X86InstrInfo : public X86GenInstrInfo {
131 X86TargetMachine &TM;
132 const X86RegisterInfo RI;
133
134 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
135 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
136 ///
137 typedef DenseMap<unsigned,
138 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
139 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
140 RegOp2MemOpTableType RegOp2MemOpTable0;
141 RegOp2MemOpTableType RegOp2MemOpTable1;
142 RegOp2MemOpTableType RegOp2MemOpTable2;
143 RegOp2MemOpTableType RegOp2MemOpTable3;
144
145 /// MemOp2RegOpTable - Load / store unfolding opcode map.
146 ///
147 typedef DenseMap<unsigned,
148 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
149 MemOp2RegOpTableType MemOp2RegOpTable;
150
151 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
152 MemOp2RegOpTableType &M2RTable,
153 unsigned RegOp, unsigned MemOp, unsigned Flags);
154
155 public:
156 explicit X86InstrInfo(X86TargetMachine &tm);
157
158 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
159 /// such, whenever a client has an instance of instruction info, it should
160 /// always be able to get register info as well (through this method).
161 ///
getRegisterInfo()162 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
163
164 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
165 /// extension instruction. That is, it's like a copy where it's legal for the
166 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
167 /// true, then it's expected the pre-extension value is available as a subreg
168 /// of the result register. This also returns the sub-register index in
169 /// SubIdx.
170 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
171 unsigned &SrcReg, unsigned &DstReg,
172 unsigned &SubIdx) const;
173
174 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
175 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
176 /// stack locations as well. This uses a heuristic so it isn't
177 /// reliable for correctness.
178 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
179 int &FrameIndex) const;
180
181 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
182 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
183 /// stack locations as well. This uses a heuristic so it isn't
184 /// reliable for correctness.
185 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
186 int &FrameIndex) const;
187
188 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
189 AliasAnalysis *AA) const;
190 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
191 unsigned DestReg, unsigned SubIdx,
192 const MachineInstr *Orig,
193 const TargetRegisterInfo &TRI) const;
194
195 /// convertToThreeAddress - This method must be implemented by targets that
196 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
197 /// may be able to convert a two-address instruction into a true
198 /// three-address instruction on demand. This allows the X86 target (for
199 /// example) to convert ADD and SHL instructions into LEA instructions if they
200 /// would require register copies due to two-addressness.
201 ///
202 /// This method returns a null pointer if the transformation cannot be
203 /// performed, otherwise it returns the new instruction.
204 ///
205 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
206 MachineBasicBlock::iterator &MBBI,
207 LiveVariables *LV) const;
208
209 /// commuteInstruction - We have a few instructions that must be hacked on to
210 /// commute them.
211 ///
212 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
213
214 // Branch analysis.
215 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
216 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
217 MachineBasicBlock *&FBB,
218 SmallVectorImpl<MachineOperand> &Cond,
219 bool AllowModify) const;
220 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
221 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
222 MachineBasicBlock *FBB,
223 const SmallVectorImpl<MachineOperand> &Cond,
224 DebugLoc DL) const;
225 virtual bool canInsertSelect(const MachineBasicBlock&,
226 const SmallVectorImpl<MachineOperand> &Cond,
227 unsigned, unsigned, int&, int&, int&) const;
228 virtual void insertSelect(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator MI, DebugLoc DL,
230 unsigned DstReg,
231 const SmallVectorImpl<MachineOperand> &Cond,
232 unsigned TrueReg, unsigned FalseReg) const;
233 virtual void copyPhysReg(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MI, DebugLoc DL,
235 unsigned DestReg, unsigned SrcReg,
236 bool KillSrc) const;
237 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
238 MachineBasicBlock::iterator MI,
239 unsigned SrcReg, bool isKill, int FrameIndex,
240 const TargetRegisterClass *RC,
241 const TargetRegisterInfo *TRI) const;
242
243 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
244 SmallVectorImpl<MachineOperand> &Addr,
245 const TargetRegisterClass *RC,
246 MachineInstr::mmo_iterator MMOBegin,
247 MachineInstr::mmo_iterator MMOEnd,
248 SmallVectorImpl<MachineInstr*> &NewMIs) const;
249
250 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
251 MachineBasicBlock::iterator MI,
252 unsigned DestReg, int FrameIndex,
253 const TargetRegisterClass *RC,
254 const TargetRegisterInfo *TRI) const;
255
256 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
257 SmallVectorImpl<MachineOperand> &Addr,
258 const TargetRegisterClass *RC,
259 MachineInstr::mmo_iterator MMOBegin,
260 MachineInstr::mmo_iterator MMOEnd,
261 SmallVectorImpl<MachineInstr*> &NewMIs) const;
262
263 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
264
265 virtual
266 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
267 int FrameIx, uint64_t Offset,
268 const MDNode *MDPtr,
269 DebugLoc DL) const;
270
271 /// foldMemoryOperand - If this target supports it, fold a load or store of
272 /// the specified stack slot into the specified machine instruction for the
273 /// specified operand(s). If this is possible, the target should perform the
274 /// folding and return true, otherwise it should return false. If it folds
275 /// the instruction, it is likely that the MachineInstruction the iterator
276 /// references has been changed.
277 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
278 MachineInstr* MI,
279 const SmallVectorImpl<unsigned> &Ops,
280 int FrameIndex) const;
281
282 /// foldMemoryOperand - Same as the previous version except it allows folding
283 /// of any load and store from / to any address, not just from a specific
284 /// stack slot.
285 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
286 MachineInstr* MI,
287 const SmallVectorImpl<unsigned> &Ops,
288 MachineInstr* LoadMI) const;
289
290 /// canFoldMemoryOperand - Returns true if the specified load / store is
291 /// folding is possible.
292 virtual bool canFoldMemoryOperand(const MachineInstr*,
293 const SmallVectorImpl<unsigned> &) const;
294
295 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
296 /// a store or a load and a store into two or more instruction. If this is
297 /// possible, returns true as well as the new instructions by reference.
298 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
299 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
300 SmallVectorImpl<MachineInstr*> &NewMIs) const;
301
302 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
303 SmallVectorImpl<SDNode*> &NewNodes) const;
304
305 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
306 /// instruction after load / store are unfolded from an instruction of the
307 /// specified opcode. It returns zero if the specified unfolding is not
308 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
309 /// index of the operand which will hold the register holding the loaded
310 /// value.
311 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
312 bool UnfoldLoad, bool UnfoldStore,
313 unsigned *LoadRegIndex = 0) const;
314
315 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
316 /// to determine if two loads are loading from the same base address. It
317 /// should only return true if the base pointers are the same and the
318 /// only differences between the two addresses are the offset. It also returns
319 /// the offsets by reference.
320 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
321 int64_t &Offset1, int64_t &Offset2) const;
322
323 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
324 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
325 /// be scheduled togther. On some targets if two loads are loading from
326 /// addresses in the same cache line, it's better if they are scheduled
327 /// together. This function takes two integers that represent the load offsets
328 /// from the common base address. It returns true if it decides it's desirable
329 /// to schedule the two loads together. "NumLoads" is the number of loads that
330 /// have already been scheduled after Load1.
331 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
332 int64_t Offset1, int64_t Offset2,
333 unsigned NumLoads) const;
334
335 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
336
337 virtual
338 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
339
340 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
341 /// instruction that defines the specified register class.
342 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
343
isX86_64ExtendedReg(const MachineOperand & MO)344 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
345 if (!MO.isReg()) return false;
346 return X86II::isX86_64ExtendedReg(MO.getReg());
347 }
348
349 /// getGlobalBaseReg - Return a virtual register initialized with the
350 /// the global base register value. Output instructions required to
351 /// initialize the register in the function entry block, if necessary.
352 ///
353 unsigned getGlobalBaseReg(MachineFunction *MF) const;
354
355 std::pair<uint16_t, uint16_t>
356 getExecutionDomain(const MachineInstr *MI) const;
357
358 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
359
360 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
361 const TargetRegisterInfo *TRI) const;
362 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
363 const TargetRegisterInfo *TRI) const;
364
365 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
366 MachineInstr* MI,
367 unsigned OpNum,
368 const SmallVectorImpl<MachineOperand> &MOs,
369 unsigned Size, unsigned Alignment) const;
370
371 bool isHighLatencyDef(int opc) const;
372
373 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
374 const MachineRegisterInfo *MRI,
375 const MachineInstr *DefMI, unsigned DefIdx,
376 const MachineInstr *UseMI, unsigned UseIdx) const;
377
378 /// analyzeCompare - For a comparison instruction, return the source registers
379 /// in SrcReg and SrcReg2 if having two register operands, and the value it
380 /// compares against in CmpValue. Return true if the comparison instruction
381 /// can be analyzed.
382 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
383 unsigned &SrcReg2,
384 int &CmpMask, int &CmpValue) const;
385
386 /// optimizeCompareInstr - Check if there exists an earlier instruction that
387 /// operates on the same source operands and sets flags in the same way as
388 /// Compare; remove Compare if possible.
389 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
390 unsigned SrcReg2, int CmpMask, int CmpValue,
391 const MachineRegisterInfo *MRI) const;
392
393 /// optimizeLoadInstr - Try to remove the load by folding it to a register
394 /// operand at the use. We fold the load instructions if and only if the
395 /// def and use are in the same BB. We only look at one load and see
396 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
397 /// defined by the load we are trying to fold. DefMI returns the machine
398 /// instruction that defines FoldAsLoadDefReg, and the function returns
399 /// the machine instruction generated due to folding.
400 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
401 const MachineRegisterInfo *MRI,
402 unsigned &FoldAsLoadDefReg,
403 MachineInstr *&DefMI) const;
404
405 private:
406 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
407 MachineFunction::iterator &MFI,
408 MachineBasicBlock::iterator &MBBI,
409 LiveVariables *LV) const;
410
411 /// isFrameOperand - Return true and the FrameIndex if the specified
412 /// operand and follow operands form a reference to the stack frame.
413 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
414 int &FrameIndex) const;
415 };
416
417 } // End llvm namespace
418
419 #endif
420