| /external/llvm/test/CodeGen/X86/ |
| D | 2009-11-13-VirtRegRewriterBug.ll | 9 %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; <i640> [#uses=1]
31 %mask271.masked.masked.masked.masked.masked.masked.masked = or i256 0, undef ; <i256> [#uses=2]
32 …%mask266.masked.masked.masked.masked.masked.masked = or i256 %mask271.masked.masked.masked.masked.…
33 %mask241.masked = or i256 undef, undef ; <i256> [#uses=1]
53 …%tmp211 = lshr i256 %mask271.masked.masked.masked.masked.masked.masked.masked, 112 ; <i256> [#uses…
55 %tmp208 = lshr i256 %mask266.masked.masked.masked.masked.masked.masked, 128 ; <i256> [#uses=1]
60 %tmp193 = lshr i256 %mask241.masked, 208 ; <i256> [#uses=1]
97 %tmp101 = lshr i640 %mask133.masked.masked.masked.masked.masked.masked, 256 ; <i640> [#uses=1]
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| D | narrow-shl-load.ll | 19 %shl15.masked = and i64 %shl15, 4294967294
20 %and17 = or i64 %shl15.masked, %conv11
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | rlwinm2.ll | 25 %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1]
26 %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1]
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | bfi.ll | 58 %b.masked = and i32 %b, -2
59 %and3 = or i32 %b.masked, %and
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield.ll | 186 %masked = and i32 %shifted, 7
187 ret i32 %masked
196 %masked = and i64 %shifted, 1023
197 ret i64 %masked
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| D | bitfield-insert.ll | 18 %f.sroa.0.0.insert.ext.masked = and i32 %tmp.sroa.0.0.extract.trunc, 135
19 %1 = or i32 %f.sroa.0.0.insert.ext.masked, %0
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| /external/llvm/test/Transforms/InstCombine/ |
| D | 2013-03-05-Combine-BitcastTy-Into-Alloca.ll | 27 %bf.value.masked = and i96 %bf.value, 4294967232
30 %bf.clear4 = or i96 %bf.shl3, %bf.value.masked
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| /external/oprofile/events/i386/athlon/ |
| D | events | 24 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED : Interrupts masked cycles (…
25 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_PENDING : Interrupts masked …
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2009-10-21-InvalidFNeg.ll | 28 %mask.masked = or i512 %tmp124, %tmp100 ; <i512> [#uses=1]
38 %tmp86 = lshr i512 %mask.masked, 256 ; <i512> [#uses=1]
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| D | fpcmp-opt.ll | 28 ; If one side is zero, the other size sign bit is masked off to allow
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| D | 2008-04-11-PHIofImpDef.ll | 2905 %tmp4253.masked.i = and i32 %tmp4253.i, 65535 ; <i32> [#uses=1]
2910 %tmp4262.masked.i = and i32 %tmp4262.i188, 64512 ; <i32> [#uses=1]
2911 %tmp42665693.masked.i = or i32 %tmp4262.masked.i, %tmp4210.i ; <i32> [#uses=1]
2914 …%tmp42665693.masked.pn.i = phi i32 [ %tmp42665693.masked.i, %bb4259.i ], [ %tmp4253.masked.i, %bb4…
2916 %tmp100.0.i = or i32 %tmp4268.pn.i, %tmp42665693.masked.pn.i ; <i32> [#uses=0]
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| /external/valgrind/main/gdbserver_tests/ |
| D | nlsigvgdb.vgtest | 4 # But if this signal is masked, then vgdb does not recuperate the control
|
| /external/elfutils/libcpu/ |
| D | i386_disasm.c | 405 uint_fast8_t masked = *codep++ & *curr++; in i386_disasm() local
406 if (masked != *curr++) in i386_disasm()
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| /external/oprofile/events/x86-64/family11h/ |
| D | events | 94 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
95 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
|
| /external/oprofile/events/x86-64/hammer/ |
| D | events | 89 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
90 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
|
| /external/valgrind/main/docs/internals/ |
| D | arm_thumb_notes_gdbserver.txt | 27 must be masked.
|
| /external/chromium/chrome/browser/ui/gtk/ |
| D | gtk_theme_service.cc | 212 SkBitmap masked = SkBitmapOperations::CreateMaskedBitmap( in BuildIconFromIDRWithColor() local
216 GdkPixbuf* pixbuf = gfx::GdkPixbufFromSkBitmap(&masked); in BuildIconFromIDRWithColor()
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| /external/llvm/test/Transforms/SimplifyCFG/X86/ |
| D | switch_to_lookup_table.ll | 99 ; CHECK-NEXT: %switch.masked = trunc i32 %switch.downshift to i8
104 ; CHECK-NEXT: %a.0 = phi i8 [ %switch.masked, %switch.lookup ], [ 7, %entry ]
236 ; CHECK-NEXT: %switch.masked = trunc i59 %switch.downshift to i1
239 ; CHECK-NEXT: %1 = phi i1 [ true, %entry ], [ %switch.masked, %switch.lookup ], [ false, %switch.ea…
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| /external/oprofile/events/x86-64/family10/ |
| D | events | 112 …rs:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
113 …INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pe…
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| /external/llvm/lib/Target/PowerPC/ |
| D | README.txt | 565 %tmp.masked = and i32 %tmp, 2147483648 ; <uint> [#uses=1]
566 %tmp11 = or i32 %tmp1415, %tmp.masked ; <uint> [#uses=1]
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| /external/oprofile/events/i386/nehalem/ |
| D | unit_masks | 78 0x02 cycles_masked Number of cycles interrupt are masked
79 0x04 cycles_pending_and_masked Number of cycles interrupts are pending and masked
|
| /external/bison/tests/ |
| D | conflicts.at | 765 # In this precise case (a reduction is masked by the default
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| /external/llvm/lib/Target/ |
| D | README.txt | 1535 %.masked = and i8 %a, 64 ; <i8> [#uses=1]
1538 %3 = or i8 %2, %.masked ; <i8> [#uses=1]
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| /external/valgrind/main/VEX/priv/ |
| D | guest_arm_toIR.c | 947 IRTemp masked = newTemp(Ity_I32); in put_GEFLAG32() local
948 assign(masked, binop(Iop_Shr32, e, mkU8(lowbits_to_ignore))); in put_GEFLAG32()
951 case 0: putMiscReg32(OFFB_GEFLAG0, mkexpr(masked), condT); break; in put_GEFLAG32()
952 case 1: putMiscReg32(OFFB_GEFLAG1, mkexpr(masked), condT); break; in put_GEFLAG32()
953 case 2: putMiscReg32(OFFB_GEFLAG2, mkexpr(masked), condT); break; in put_GEFLAG32()
954 case 3: putMiscReg32(OFFB_GEFLAG3, mkexpr(masked), condT); break; in put_GEFLAG32()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 1336 // setcc instead and earlier I had implemented setcc first so may have masked
|