Searched refs:outb (Results 1 – 25 of 49) sorted by relevance
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111 outb(D8390_COMMAND_RD2 |113 outb(cnt, eth_nic_base + D8390_P0_RBCR0);114 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);115 outb(src, eth_nic_base + D8390_P0_RSAR0);116 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);117 outb(D8390_COMMAND_RD0 |121 outb(src & 0xff, eth_asic_base + _3COM_DALSB);122 outb(src >> 8, eth_asic_base + _3COM_DAMSB);123 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);144 outb(t503_output, eth_asic_base + _3COM_CR);[all …]
188 outb(RS_VALID_BITS, EDLC_RCLR); /* Clear all pending Rcv interrupts */ in reset_receiver()189 outb(MM_EN_RCV, IE_MMODE); /* Enable rcv */ in reset_receiver()200 outb(RS_RESET, EDLC_RESET); /* Hold up EDLC_RESET while configing board */ in ni5010_reset()201 outb(0, IE_RESET); /* Hardware reset of ni5010 board */ in ni5010_reset()202 outb(0, EDLC_XMASK); /* Disable all Xmt interrupts */ in ni5010_reset()203 outb(0, EDLC_RMASK); /* Disable all Rcv interrupt */ in ni5010_reset()204 outb(0xFF, EDLC_XCLR); /* Clear all pending Xmt interrupts */ in ni5010_reset()205 outb(0xFF, EDLC_RCLR); /* Clear all pending Rcv interrupts */ in ni5010_reset()206 outb(XMD_LBC, EDLC_XMODE); /* Only loopback xmits */ in ni5010_reset()209 outb(nic->node_addr[i], EDLC_ADDR + i); in ni5010_reset()[all …]
261 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40);265 outb(SEL_RESET_CMD, ioaddr); \271 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)274 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)277 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)307 outb(temp_reg & 0xEF, ioaddr + eeprom_reg); in eepro_reset()309 outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i); in eepro_reset()[all …]
118 outb(CARD_DISABLE, ioaddr + DLCR_ENABLE); in tiara_reset()119 outb(CLEAR_STATUS, ioaddr + DLCR_XMIT_STAT); in tiara_reset()120 outb(NO_TX_IRQS, ioaddr + DLCR_XMIT_MASK); in tiara_reset()121 outb(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT); in tiara_reset()122 outb(XMIT_MODE, ioaddr + DLCR_XMIT_MODE); in tiara_reset()123 outb(RECV_MODE, ioaddr + DLCR_RECV_MODE); in tiara_reset()129 outb(nic->node_addr[i], ioaddr + DLCR_NODE_ID + i); in tiara_reset()130 outb(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT); in tiara_reset()131 outb(CARD_ENABLE, ioaddr + DLCR_ENABLE); in tiara_reset()180 outb(p[s-1], ioaddr + BMPR_MEM_PORT); in tiara_transmit()[all …]
16 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); in load_timer2()17 outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT); in load_timer2()18 outb(ticks & 0xFF, TIMER2_PORT); in load_timer2()19 outb(ticks >> 8, TIMER2_PORT); in load_timer2()50 outb((inb(0x61) & ~0x02) | 0x01, 0x61); in calibrate_tsc()59 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ in calibrate_tsc()60 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ in calibrate_tsc()61 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ in calibrate_tsc()
311 outb(0, ioaddr + I82586_ATTN); in ack_status()328 outb(0x20, ioaddr + MISC_CTRL); in i82586_reset()345 outb(0xA0, ioaddr + MISC_CTRL); in i82586_reset()350 outb(0, ioaddr + I82586_ATTN); in i82586_reset()363 outb(0, ioaddr + I82586_ATTN); in i82586_reset()367 outb(0x80, ioaddr + MISC_CTRL); in i82586_reset()488 outb(0, ioaddr + I82586_ATTN); in i82586_disable()490 outb(0, ioaddr + NI52_RESET); in i82586_disable()524 outb(0x01, ioaddr + MISC_CTRL); in t507_probe1()549 outb(0x00, ID_PORT); in t507_probe()[all …]
200 outb(0x00, ioaddr + Config1); in rtl8139_probe()258 outb(EE_ENB & ~EE_CS, ee_addr); in read_eeprom()259 outb(EE_ENB, ee_addr); in read_eeprom()264 outb(EE_ENB | dataval, ee_addr); in read_eeprom()266 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); in read_eeprom()269 outb(EE_ENB, ee_addr); in read_eeprom()273 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); in read_eeprom()276 outb(EE_ENB, ee_addr); in read_eeprom()281 outb(~EE_CS, ee_addr); in read_eeprom()289 outb(CmdReset, ioaddr + ChipCmd); in rtl_reset()[all …]
107 outb(nic->node_addr[i], BASE + EP_W2_ADDR_0 + i); in t509_reset()190 outb(0x0, BASE + EP_W1_TX_STATUS); in t509_transmit()205 outb(*(p+s - 1), BASE + EP_W1_TX_PIO_WR_1); in t509_transmit()208 outb(0, BASE + EP_W1_TX_PIO_WR_1); /* Padding */ in t509_transmit()341 outb(al, port); in send_ID_sequence()366 outb(0x80 + offset, id_port); in get_eeprom_data()376 outb(0xc0, EP_ID_PORT); in t509_disable()477 outb(W0_P4_CMD_RESET_ADAPTER, io_base + EP_W0_CONFIG_CTRL); in t529_probe()479 outb(W0_P4_CMD_ENABLE_ADAPTER, io_base + EP_W0_CONFIG_CTRL); in t529_probe()492 outb(0xc0, id_port); /* Global reset */ in t529_probe()[all …]
751 outb (byMIICRbak & 0x7f, byMIICR); in ReadMII()754 outb (byMIIIndex, byMIIAD); in ReadMII()757 outb (inb (byMIICR) | 0x40, byMIICR); in ReadMII()771 outb (byMIIAdrbak, byMIIAD); in ReadMII()772 outb (byMIICRbak, byMIICR); in ReadMII()792 outb (byMIICRbak & 0x7f, byMIICR); in WriteMII()794 outb (byMIISetByte, byMIIAD); in WriteMII()797 outb (inb (byMIICR) | 0x40, byMIICR); in WriteMII()827 outb (inb (byMIICR) | 0x20, byMIICR); in WriteMII()838 outb (byMIIAdrbak & 0x7f, byMIIAD); in WriteMII()[all …]
109 outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i); in t595_reset()199 outb(0x0, BASE + VX_W1_TX_STATUS); in t595_transmit()215 outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1); in t595_transmit()218 outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */ in t595_transmit()
544 outb(nicsr, DEPCA_NICSR); in depca_reset()678 outb(nicsr, DEPCA_NICSR); in depca_probe1()692 outb(nicsr, DEPCA_NICSR); in depca_probe1()719 outb(nicsr |= SHE, DEPCA_NICSR); in depca_probe1()
319 outb(eth_irq, eth_nic_base + DATA_PORT); in cs89x0_reset()320 outb(0, eth_nic_base + DATA_PORT + 1); } in cs89x0_reset()324 outb((eth_mem_start >> 8) & 0xff, eth_nic_base + DATA_PORT); in cs89x0_reset()325 outb((eth_mem_start >> 24) & 0xff, eth_nic_base + DATA_PORT + 1); } } in cs89x0_reset()
197 outb(0x09 + i, 0x70); in sis630e_get_mac_addr()358 outb(EECS, ee_addr); in sis900_read_eeprom()450 outb(dataval, mdio_addr); in sis900_mdio_write()452 outb(dataval | MDC, mdio_addr); in sis900_mdio_write()469 outb(0, mdio_addr); in sis900_mdio_write()471 outb(MDC, mdio_addr); in sis900_mdio_write()
439 outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b); in a3c90x_reset()545 outb(0x00, INF_3C90X.IOAddr + regTxStatus_b); in a3c90x_transmit()562 outb(0x00, INF_3C90X.IOAddr + regTxStatus_b); in a3c90x_transmit()891 outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b); in a3c90x_probe()
40 outb (unsigned short port, unsigned char value) in outb() function50 outb (HERCULES_INDEX_REG, 0x0f); in herc_set_cursor()51 outb (0x80, 0); in herc_set_cursor()52 outb (HERCULES_DATA_REG, offset & 0xFF); in herc_set_cursor()53 outb (0x80, 0); in herc_set_cursor()55 outb (HERCULES_INDEX_REG, 0x0e); in herc_set_cursor()56 outb (0x80, 0); in herc_set_cursor()57 outb (HERCULES_DATA_REG, offset >> 8); in herc_set_cursor()58 outb (0x80, 0); in herc_set_cursor()177 outb (HERCULES_INDEX_REG, 0x0a); in hercules_setcursor()[all …]
77 outb (unsigned short port, unsigned char value) in outb() function107 outb (serial_hw_port + UART_TX, c); in serial_hw_put()113 outb (0x80, 0); in serial_hw_delay()142 outb (port + UART_IER, 0); in serial_hw_init()145 outb (port + UART_LCR, UART_DLAB); in serial_hw_init()158 outb (port + UART_DLL, div & 0xFF); in serial_hw_init()159 outb (port + UART_DLH, div >> 8); in serial_hw_init()163 outb (port + UART_LCR, status); in serial_hw_init()166 outb (port + UART_FCR, UART_ENABLE_FIFO); in serial_hw_init()169 outb (port + UART_MCR, UART_ENABLE_MODEM); in serial_hw_init()
82 outb (unsigned short port, unsigned char val) in outb() function91 outb (0x70, loc); in cmos_write_byte()92 outb (0x71, val); in cmos_write_byte()98 outb (0x70, loc); in cmos_read_byte()
66 static void outb();419 outb dx,al424 outb dx,al427 outb dx,al875 outb(VGAREG_PEL_MASK,vga_modes[line].pelmask);878 outb(VGAREG_DAC_WRITE_ADDRESS,0x00);898 {outb(VGAREG_DAC_DATA,palette[(i*3)+0]);899 outb(VGAREG_DAC_DATA,palette[(i*3)+1]);900 outb(VGAREG_DAC_DATA,palette[(i*3)+2]);903 {outb(VGAREG_DAC_DATA,0);[all …]
40 outb dx, al define83 outb dx, al define94 outb dx, al define96 outb dx, al define98 outb dx, al define100 outb dx, al define106 outb dx,al define108 outb dx,al define138 outb dx, al define
854 static void outb();1162 outb(port, val)1430 outb(base_port + UART_THR, data);1464 if (action & BIOS_PRINTF_DEBUG) outb(DEBUG_PORT, c);1465 if (action & BIOS_PRINTF_INFO) outb(INFO_PORT, c);1641 outb(PANIC_PORT2, 0x00);1754 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);1759 outb(0x80, 0x00);1773 outb(0x64, 0xaa);1777 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);[all …]
57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ in i8259_irq()64 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */ in i8259_irq()76 outb(0x0B, PIC_MASTER_ISR); /* ISR register */ in i8259_irq()
129 outb(0x02, 0x3C4); in D_BeginDirectRect()130 outb(1 << plane, 0x3C5); in D_BeginDirectRect()131 outb(4, 0x3CE); in D_BeginDirectRect()132 outb(plane, 0x3CF); in D_BeginDirectRect()193 outb(2, 0x3C4); in D_EndDirectRect()194 outb(1 << plane, 0x3C5); in D_EndDirectRect()195 outb(4, 0x3CE); in D_EndDirectRect()196 outb(plane, 0x3CF); in D_EndDirectRect()
42 outb %al,%dx // point the SC to the Map Mask65 outb %al,%dx
130 outb(0x02, 0x3C4); in D_BeginDirectRect()131 outb(1 << plane, 0x3C5); in D_BeginDirectRect()132 outb(4, 0x3CE); in D_BeginDirectRect()133 outb(plane, 0x3CF); in D_BeginDirectRect()194 outb(2, 0x3C4); in D_EndDirectRect()195 outb(1 << plane, 0x3C5); in D_EndDirectRect()196 outb(4, 0x3CE); in D_EndDirectRect()197 outb(plane, 0x3CF); in D_EndDirectRect()