Home
last modified time | relevance | path

Searched refs:sra (Results 1 – 25 of 69) sorted by relevance

123

/external/llvm/test/MC/MBlaze/
Dmblaze_shift.s39 # CHECK: sra
42 sra r1, r2
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td224 [(set GR8:$dst, (sra GR8:$src1, CL))],
228 [(set GR16:$dst, (sra GR16:$src1, CL))],
232 [(set GR32:$dst, (sra GR32:$src1, CL))],
236 [(set GR64:$dst, (sra GR64:$src1, CL))],
242 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
246 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
251 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
256 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
262 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
266 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
[all …]
/external/llvm/test/MC/Mips/
Dmips64-alu-instructions.s26 # CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
53 sra $4, $3, 7
Dmips-alu-instructions.s26 # CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
53 sra $4, $3, 7
/external/llvm/test/CodeGen/Mips/
Datomic.ll100 ; CHECK: sra $2, $[[R17]], 24
131 ; CHECK: sra $2, $[[R17]], 24
163 ; CHECK: sra $2, $[[R17]], 24
193 ; CHECK: sra $2, $[[R17]], 24
228 ; CHECK: sra $2, $[[R17]], 24
Dsra1.ll10 ; 16: sra ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
Ddsp-r2.ll235 %0 = tail call <2 x i16> @llvm.mips.precr.sra.ph.w(i32 %a0, i32 %a1, i32 15)
241 declare <2 x i16> @llvm.mips.precr.sra.ph.w(i32, i32, i32) nounwind readnone
247 %0 = tail call <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32 %a0, i32 %a1, i32 15)
253 declare <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32, i32, i32) nounwind readnone
/external/v8/test/cctest/
Dtest-disasm-mips.cc261 COMPARE(sra(a0, a1, 0), in TEST()
263 COMPARE(sra(s0, s1, 8), in TEST()
265 COMPARE(sra(t2, t3, 24), in TEST()
267 COMPARE(sra(v0, v1, 31), in TEST()
/external/webkit/Source/cmake/
DWebKitHelpers.cmake11 # GCC 4.5.1 does not implement -ftree-sra correctly
14 SET(OLD_COMPILE_FLAGS "${OLD_COMPILE_FLAGS} -fno-tree-sra")
/external/kernel-headers/original/asm-mips/
Dasm.h266 #define INT_SRA sra
303 #define LONG_SRA sra
352 #define PTR_SRA sra
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_shift.txt25 # CHECK: sra r1, r2
/external/libffi/src/alpha/
Dosf.S214 sra $0, 56, $0
239 sra $0, 48, $0
/external/llvm/test/CodeGen/X86/
Dblend-msb.ll5 ; shifting the needed bit to the MSB, and not using shl+sra.
Dvec_sdiv_to_shift.ll19 ; CHECK-NOT: sra
/external/llvm/test/Transforms/GlobalOpt/
Dglobalsra-unknown-index.ll6 ; globalopt should not sra the global, because it can't see the index.
/external/openssl/crypto/bn/asm/
Ds390x.S30 sra %r4,2 // cnt=len/4
105 sra %r4,2 // cnt=len/4
234 sra %r5,2 // len/4, use sra because it sets condition code
288 sra %r5,2 // len/4, use sra because it sets condition code
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td505 [shl, srl, sra, rotr]> {
516 [shl, srl, sra, rotr]> {
527 [shl,srl,sra,rotr]> {
538 [shl,srl,sra,rotr]> {
3671 (sra GPR:$Rm, (i32 16))))]>,
3676 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3682 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3683 (sra GPR:$Rm, (i32 16))))]>,
3688 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3694 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
[all …]
DARMInstrThumb2.td47 [shl,srl,sra,rotr]> {
2163 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2538 (sra rGPR:$Rm, (i32 16))))]>,
2550 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2563 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2564 (sra rGPR:$Rm, (i32 16))))]>,
2576 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2589 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2590 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2621 (sra rGPR:$Rm, (i32 16)))))]>,
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td403 def ShiftRAV2I64 : VecShiftOp<V2AsmStr<"shr.s64">, sra, V2I64Regs, V2I32Regs,
405 def ShiftRAV2I32 : VecShiftOp<V2AsmStr<"shr.s32">, sra, V2I32Regs, V2I32Regs,
407 def ShiftRAV4I32 : VecShiftOp<V4AsmStr<"shr.s32">, sra, V4I32Regs, V4I32Regs,
409 def ShiftRAV2I16 : VecShiftOp<V2AsmStr<"shr.s16">, sra, V2I16Regs, V2I32Regs,
411 def ShiftRAV4I16 : VecShiftOp<V4AsmStr<"shr.s16">, sra, V4I16Regs, V4I32Regs,
413 def ShiftRAV2I8 : VecShiftOp<V2AsmStr<"shr.s16">, sra, V2I8Regs, V2I32Regs,
415 def ShiftRAV4I8 : VecShiftOp<V4AsmStr<"shr.s16">, sra, V4I8Regs, V4I32Regs,
451 def : Pat<(sra V2I16Regs:$src1, V2I16Regs:$src2),
453 def : Pat<(sra V2I8Regs:$src1, V2I8Regs:$src2),
455 def : Pat<(sra V2I64Regs:$src1, V2I64Regs:$src2),
[all …]
/external/v8/src/mips/
Dcode-stubs-mips.cc468 __ sra(source_, source_, kSmiTagSize); in Generate() local
524 __ sra(scratch1, a0, kSmiTagSize); in LoadSmis() local
527 __ sra(scratch1, a1, kSmiTagSize); in LoadSmis() local
1245 __ sra(at, rhs, kSmiTagSize); in EmitSmiNonsmiComparison() local
1284 __ sra(at, lhs, kSmiTagSize); in EmitSmiNonsmiComparison() local
1591 __ sra(mask, mask, kSmiTagSize + 1); in GenerateLookupNumberStringCache() local
1643 __ sra(scratch, object, 1); // Shift away the tag. in GenerateLookupNumberStringCache() local
1695 __ sra(a1, a1, 1); in Generate() local
1696 __ sra(a0, a0, 1); in Generate() local
2411 __ sra(scratch1, scratch1, 31); in GenerateSmiSmiOperation() local
[all …]
/external/valgrind/main/none/tests/mips32/
DMIPS32int.stdout.exp-mips32838 sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
839 sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
840 sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
841 sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
842 sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
843 sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
844 sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
845 sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
846 sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
847 sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
[all …]
DMIPS32int.stdout.exp-BE950 sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
951 sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
952 sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
953 sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
954 sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
955 sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
956 sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
957 sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
958 sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
959 sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
[all …]
DMIPS32int.stdout.exp950 sra $t0, $t1, 0x00000000 :: rt 0x00000001 rs 0x00000001, imm 0x31415927
951 sra $t0, $t1, 0x00000001 :: rt 0x18a0ac93 rs 0x31415927, imm 0x00000001
952 sra $t0, $t1, 0x00000002 :: rt 0x0c505649 rs 0x31415927, imm 0x00000002
953 sra $t0, $t1, 0x0000000F :: rt 0x00006282 rs 0x31415927, imm 0x0000000f
954 sra $t0, $t1, 0x00000010 :: rt 0x00000000 rs 0x00000010, imm 0x00000010
955 sra $t0, $t1, 0x0000001F :: rt 0x00000000 rs 0x00000010, imm 0x31415927
956 sra $t0, $t1, 0x00000009 :: rt 0x0018a0ac rs 0x31415927, imm 0x00000009
957 sra $t0, $t1, 0x0000000A :: rt 0x000c5056 rs 0x31415927, imm 0x0000000a
958 sra $t0, $t1, 0x00000000 :: rt 0x00088000 rs 0x00088000, imm 0x0000000a
959 sra $t0, $t1, 0x00000001 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
[all …]
/external/openssl/crypto/
Dsparccpuid.S202 sra %i2,%g0,%i0
215 sra %o0,%g0,%o0 ! we return signed int, remember?
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td107 def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
111 def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;

123