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Searched refs:v8f32 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dvec_floor.ll35 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
71 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
74 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
107 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
110 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
143 %t = call <8 x float> @llvm.rint.v8f32(<8 x float> %p)
146 declare <8 x float> @llvm.rint.v8f32(<8 x float> %p)
179 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
182 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dvec_fabs.ll35 %t = call <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
38 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
/external/llvm/test/CodeGen/PowerPC/
Dvec_rounding.ll107 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
110 %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
126 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
129 %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
145 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
148 %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
164 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
167 %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
Dvec_sqrt.ll11 declare <8 x float> @llvm.sqrt.v8f32(<8 x float> %val)
40 %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
/external/llvm/lib/Target/X86/
DX86InstrFMA.td78 memopv8f32, X86Fmadd, v4f32, v8f32>;
80 memopv8f32, X86Fmsub, v4f32, v8f32>;
83 v4f32, v8f32>;
86 v4f32, v8f32>;
105 memopv8f32, X86Fnmadd, v4f32, v8f32>;
107 memopv8f32, X86Fnmsub, v4f32, v8f32>;
340 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
342 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
344 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
346 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
[all …]
DX86TargetTransformInfo.cpp251 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 }, in getCastInstrCost()
253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 }, in getCastInstrCost()
255 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 }, in getCastInstrCost()
297 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
DX86CallingConv.td49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
99 CCIfType<[v8f32, v4f64, v8i32, v4i64],
210 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
227 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
247 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
342 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
350 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
464 CCIfType<[v8f32, v4f64, v8i32, v4i64],
DX86InstrSSE.td253 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
254 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
276 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
286 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
332 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
[all …]
DX86InstrFragmentsSIMD.td254 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
306 (v8f32 (alignedload256 node:$ptr))>;
334 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
DX86ISelLowering.cpp1081 addRegisterClass(MVT::v8f32, &X86::VR256RegClass); in X86TargetLowering()
1085 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); in X86TargetLowering()
1089 setOperationAction(ISD::FADD, MVT::v8f32, Legal); in X86TargetLowering()
1090 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); in X86TargetLowering()
1091 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); in X86TargetLowering()
1092 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); in X86TargetLowering()
1093 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); in X86TargetLowering()
1094 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal); in X86TargetLowering()
1095 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); in X86TargetLowering()
1096 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal); in X86TargetLowering()
[all …]
DX86RegisterInfo.td412 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrCompiler.td872 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
268 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
/external/llvm/include/llvm/CodeGen/
DValueTypes.h99 v8f32 = 44, // 8 x f32 enumerator
218 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
293 case v8f32: in getVectorElementType()
321 case v8f32: in getVectorNumElements()
397 case v8f32: in getSizeInBits()
526 if (NumElements == 8) return MVT::v8f32; in getVectorVT()
DValueTypes.td68 def v8f32 : ValueType<256, 44>; // 8 x f32 vector value
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp326 DecodeSHUFPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
364 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
400 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask); in EmitAnyX86InstComments()
416 DecodePSHUFMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
/external/llvm/lib/IR/
DValueTypes.cpp162 case MVT::v8f32: return "v8f32"; in getEVTString()
225 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8); in getTypeForEVT()
/external/llvm/test/CodeGen/ARM/
DfusedMAC.ll215 …%call = tail call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c) noun…
224 declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp54 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass); in SITargetLowering()
62 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
DSIRegisterInfo.td167 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 256, (add VGPR_256)>;
DSIInstructions.td1330 f32, v8f32, VReg_256, Index, !cast<SubRegIndex>(sub#Index)
1333 f32, v8f32, VReg_32, VReg_256, Index, !cast<SubRegIndex>(sub#Index)
1359 def : Vector8_Build <v8f32, VReg_256, f32, VReg_32>;
1590 defm : SI_INDIRECT_Pattern <VReg_256, v8f32, SI_INDIRECT_DST_V8>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp103 case MVT::v8f32: return "MVT::v8f32"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td158 def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float