Searched refs:CPSR_M (Results 1 – 4 of 4) sorted by relevance
263 #define CPSR_M (0x1f) macro466 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; in cpu_mmu_index()474 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR; in is_cpu_user()531 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; in cpu_get_tb_cpu_state()
509 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { in cpsr_write()510 switch_mode(env, val & CPSR_M); in cpsr_write()668 old_mode = env->uncached_cpsr & CPSR_M; in switch_mode()864 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()880 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { in do_interrupt()918 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) { in do_interrupt()932 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) { in do_interrupt()952 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; in do_interrupt()1456 || (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) in HELPER()1711 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { in HELPER()[all …]
127 env->uncached_cpsr = val & CPSR_M; in cpu_load()
6646 mask |= CPSR_M; in disas_arm_insn()