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Searched refs:CPUState (Results 1 – 25 of 75) sorted by relevance

123

/external/qemu/
Dkvm.h40 int kvm_init_vcpu(CPUState *env);
43 int kvm_cpu_exec(CPUState *env);
63 int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
65 int kvm_remove_breakpoint(CPUState *current_env, target_ulong addr,
67 void kvm_remove_all_breakpoints(CPUState *current_env);
68 int kvm_update_guest_debug(CPUState *env, unsigned long reinject_trap);
79 int kvm_vcpu_ioctl(CPUState *env, int type, ...);
81 int kvm_get_mp_state(CPUState *env);
82 int kvm_put_mp_state(CPUState *env);
86 int kvm_arch_post_run(CPUState *env, struct kvm_run *run);
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Dmonitor.c85 CPUState *mon_cpu;
112 CPUState *cenv; in do_inject_mce()
359 CPUState *env; in mon_set_cpu()
370 static CPUState *mon_get_cpu(void) in mon_get_cpu()
381 CPUState *env; in do_info_registers()
396 CPUState *env; in do_info_cpus()
455 CPUState *env; in do_info_cpu_stats()
639 CPUState *env; in memory_dump()
840 CPUState *env; in do_memory_save()
1245 CPUState *env; in tlb_info()
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Dhax.h16 int hax_init_vcpu(CPUState *env);
18 int hax_vcpu_exec(CPUState *env);
21 void hax_vcpu_sync_state(CPUState *env, int modified);
26 int hax_vcpu_emulation_mode(CPUState *env);
27 int hax_stop_emulation(CPUState *env);
28 int hax_stop_translate(CPUState *env);
29 int hax_arch_get_registers(CPUState *env);
30 void hax_raise_event(CPUState *env);
Dgdbstub.h14 typedef void (*gdb_syscall_complete_cb)(CPUState *env,
19 void gdb_set_stop_cpu(CPUState *env);
20 void gdb_exit(CPUState *, int);
23 int gdb_handlesig (CPUState *, int);
24 void gdb_signalled(CPUState *, int);
25 void gdbserver_fork(CPUState *);
28 typedef int (*gdb_reg_cb)(CPUState *env, uint8_t *buf, int reg);
29 void gdb_register_coprocessor(CPUState *env,
Dcpus.c35 static CPUState *cur_cpu;
36 static CPUState *next_cpu;
42 CPUState *env; in hw_error()
70 static int cpu_can_run(CPUState *env) in cpu_can_run()
79 static int cpu_has_work(CPUState *env) in cpu_has_work()
94 CPUState *env; in tcg_has_work()
191 CPUState *env = _env; in qemu_init_vcpu()
222 CPUState *env = cpu_single_env; in qemu_notify_event()
308 static void qemu_wait_io_event(CPUState *env) in qemu_wait_io_event()
331 static int qemu_cpu_exec(CPUState *env);
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Dexec-all.h70 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
71 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
72 void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb, int pc_pos);
76 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
79 CPUState *env, unsigned long searched_pc);
80 void cpu_resume_from_signal(CPUState *env1, void *puc);
81 void cpu_io_recompile(CPUState *env, void *retaddr);
82 TranslationBlock *tb_gen_code(CPUState *env,
85 void cpu_exec_init(CPUState *env);
91 void tlb_flush_page(CPUState *env, target_ulong addr);
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Dcpu-all.h765 CPUState *cpu_copy(CPUState *env);
766 CPUState *qemu_get_cpu(int cpu);
770 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
772 void cpu_dump_statistics(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
775 void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
777 extern CPUState *first_cpu;
778 extern CPUState *cpu_single_env;
837 void cpu_interrupt(CPUState *s, int mask);
838 void cpu_reset_interrupt(CPUState *env, int mask);
840 void cpu_exit(CPUState *s);
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Dsoftmmu-semi.h10 static inline uint32_t softmmu_tget32(CPUState *env, uint32_t addr) in softmmu_tget32()
17 static inline uint32_t softmmu_tget8(CPUState *env, uint32_t addr) in softmmu_tget8()
29 static inline void softmmu_tput32(CPUState *env, uint32_t addr, uint32_t val) in softmmu_tput32()
37 static void *softmmu_lock_user(CPUState *env, uint32_t addr, uint32_t len, in softmmu_lock_user()
48 static char *softmmu_lock_user_string(CPUState *env, uint32_t addr) in softmmu_lock_user_string()
63 static void softmmu_unlock_user(CPUState *env, void *p, target_ulong addr, in softmmu_unlock_user()
Dgen-icount.h17 tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32)); in gen_icount_start()
23 tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low)); in gen_icount_start()
39 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_start()
46 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io)); in gen_io_end()
Dkvm-all.c147 int kvm_init_vcpu(CPUState *env) in kvm_init_vcpu()
184 int kvm_put_mp_state(CPUState *env) in kvm_put_mp_state()
191 int kvm_get_mp_state(CPUState *env) in kvm_get_mp_state()
206 CPUState *env; in kvm_sync_vcpus()
516 static int kvm_handle_io(CPUState *env, uint16_t port, void *data, in kvm_handle_io()
555 static void kvm_run_coalesced_mmio(CPUState *env, struct kvm_run *run) in kvm_run_coalesced_mmio()
576 int kvm_cpu_exec(CPUState *env) in kvm_cpu_exec()
842 int kvm_vcpu_ioctl(CPUState *env, int type, ...) in kvm_vcpu_ioctl()
889 struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *env, in kvm_find_sw_breakpoint()
901 int kvm_sw_breakpoints_active(CPUState *env) in kvm_sw_breakpoints_active()
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Dgdbstub.c275 CPUState *c_cpu; /* current CPU for step/continue ops */
276 CPUState *g_cpu; /* current CPU for other ops */
277 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
513 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_read_register()
560 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i) in cpu_gdb_write_register()
638 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_read_register()
675 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_write_register()
736 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_read_register()
791 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_write_register()
866 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) in cpu_gdb_read_register()
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Dexec.c124 CPUState *first_cpu;
127 CPUState *cpu_single_env;
393 static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
538 CPUState *env = opaque; in cpu_common_save()
548 CPUState *env = opaque; in cpu_common_load()
565 CPUState *qemu_get_cpu(int cpu) in qemu_get_cpu()
567 CPUState *env = first_cpu; in qemu_get_cpu()
578 void cpu_exec_init(CPUState *env) in cpu_exec_init()
580 CPUState **penv; in cpu_exec_init()
638 void tb_flush(CPUState *env1) in tb_flush()
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/external/qemu/hw/
Dmips_timer.c8 uint32_t cpu_mips_get_random (CPUState *env) in cpu_mips_get_random()
23 uint32_t cpu_mips_get_count (CPUState *env) in cpu_mips_get_count()
33 static void cpu_mips_timer_update(CPUState *env) in cpu_mips_timer_update()
45 void cpu_mips_store_count (CPUState *env, uint32_t count) in cpu_mips_store_count()
59 void cpu_mips_store_compare (CPUState *env, uint32_t value) in cpu_mips_store_compare()
69 void cpu_mips_start_count(CPUState *env) in cpu_mips_start_count()
74 void cpu_mips_stop_count(CPUState *env) in cpu_mips_stop_count()
83 CPUState *env; in mips_timer_cb()
104 void cpu_mips_clock_init (CPUState *env) in cpu_mips_clock_init()
Dmips_int.c7 void cpu_mips_update_irq(CPUState *env) in cpu_mips_update_irq()
23 CPUState *env = (CPUState *)opaque; in cpu_mips_irq_request()
36 void cpu_mips_irq_init_cpu(CPUState *env) in cpu_mips_irq_init_cpu()
Dmips_pic.c19 CPUState *env = (CPUState *)opaque; in mips_cpu_irq_handler()
36 qemu_irq *mips_cpu_irq_init(CPUState *env) in mips_cpu_irq_init()
Darm_pic.c27 CPUState *env = (CPUState *)opaque; in arm_pic_cpu_handler()
46 qemu_irq *arm_pic_init_cpu(CPUState *env) in arm_pic_init_cpu()
Dpc.h49 int apic_init(CPUState *env);
50 int apic_accept_pic_intr(CPUState *env);
51 void apic_deliver_pic_intr(CPUState *env, int level);
52 int apic_get_interrupt(CPUState *env);
165 int cpu_is_bsp(CPUState *env);
/external/qemu/target-mips/
Dexec.h20 void dump_fpu(CPUState *env);
21 void fpu_dump_state(CPUState *env, FILE *f,
25 void cpu_mips_clock_init (CPUState *env);
26 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
36 static inline int cpu_has_work(CPUState *env) in cpu_has_work()
55 static inline int cpu_halted(CPUState *env) in cpu_halted()
66 static inline void compute_hflags(CPUState *env) in compute_hflags()
Dcpu.h8 #define CPUState struct CPUMIPSState macro
497 static inline int cpu_mmu_index (CPUState *env) in cpu_mmu_index()
502 static inline int is_cpu_user (CPUState *env) in is_cpu_user()
512 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) in cpu_clone_regs()
520 static inline int cpu_mips_hw_interrupts_pending(CPUState *env) in cpu_mips_hw_interrupts_pending()
617 uint32_t cpu_mips_get_random (CPUState *env);
618 uint32_t cpu_mips_get_count (CPUState *env);
619 void cpu_mips_store_count (CPUState *env, uint32_t value);
620 void cpu_mips_store_compare (CPUState *env, uint32_t value);
621 void cpu_mips_start_count(CPUState *env);
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Dtranslate.c557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_load_srsgpr()
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); in gen_store_srsgpr()
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_load_fpr32()
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_store_fpr32()
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_load_fpr32h()
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_store_fpr32h()
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); in gen_load_fpr64()
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); in gen_store_fpr64()
773 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) in restore_cpu_state()
871 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags) in check_insn()
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/external/qemu/target-i386/
Dhax-i386.h58 hax_fd hax_vcpu_get_fd(CPUState *env);
63 int hax_inject_interrupt(CPUState *env, int vector);
67 int hax_sync_vcpu_state(CPUState *env, struct vcpu_state_t *state, int set);
68 int hax_sync_msr(CPUState *env, struct hax_msr_data *msrs, int set);
69 int hax_sync_fpu(CPUState *env, struct fx_layout *fl, int set);
Dhax-all.c42 int hax_vcpu_emulation_mode(CPUState *env) in hax_vcpu_emulation_mode()
47 static int hax_prepare_emulation(CPUState *env) in hax_prepare_emulation()
61 static int hax_stop_tbloop(CPUState *env) in hax_stop_tbloop()
81 int hax_stop_emulation(CPUState *env) in hax_stop_emulation()
97 int hax_stop_translate(CPUState *env) in hax_stop_translate()
114 hax_fd hax_vcpu_get_fd(CPUState *env) in hax_vcpu_get_fd()
236 int hax_vcpu_destroy(CPUState *env) in hax_vcpu_destroy()
259 int hax_init_vcpu(CPUState *env) in hax_init_vcpu()
398 int hax_handle_fastmmio(CPUState *env, struct hax_fastmmio *hft) in hax_handle_fastmmio()
423 int hax_handle_io(CPUState *env, uint32_t df, uint16_t port, int direction, in hax_handle_io()
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Dkvm.c70 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg) in kvm_arch_get_supported_cpuid()
119 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg) in kvm_arch_get_supported_cpuid()
130 int kvm_arch_init_vcpu(CPUState *env) in kvm_arch_init_vcpu()
208 static int kvm_has_msr_star(CPUState *env) in kvm_has_msr_star()
330 static int kvm_getput_regs(CPUState *env, int set) in kvm_getput_regs()
369 static int kvm_put_fpu(CPUState *env) in kvm_put_fpu()
387 static int kvm_put_sregs(CPUState *env) in kvm_put_sregs()
446 static int kvm_put_msrs(CPUState *env) in kvm_put_msrs()
475 static int kvm_get_fpu(CPUState *env) in kvm_get_fpu()
496 int kvm_get_sregs(CPUState *env) in kvm_get_sregs()
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/external/qemu/target-arm/
Dexec.h35 static inline int cpu_has_work(CPUState *env) in cpu_has_work()
41 static inline int cpu_halted(CPUState *env) { in cpu_halted()
59 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) in cpu_pc_from_tb()
Dhelper.c323 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg) in vfp_gdb_get_reg()
350 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg) in vfp_gdb_set_reg()
576 void do_interrupt (CPUState *env) in do_interrupt()
581 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, in cpu_arm_handle_mmu_fault()
595 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) in HELPER()
600 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) in HELPER()
607 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) in HELPER()
612 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) in HELPER()
618 void switch_mode(CPUState *env, int mode) in switch_mode()
624 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) in HELPER()
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