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Searched refs:EXTRACT_SUBREG (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsDerived.td20 (EXTRACT_SUBREG
22 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
24 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
32 (EXTRACT_SUBREG
34 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
35 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
DHexagonSelectCCInfo.td104 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
105 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
107 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
108 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
116 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
117 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
120 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
121 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
DHexagonInstrInfo.td395 (COMBINE_lh (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_hireg),
396 (EXTRACT_SUBREG (i64 DoubleRegs:$a), subreg_loreg))>;
2587 (i64 (SXTW (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg))))>;
2591 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2596 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
2644 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2646 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2649 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
2651 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
2667 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
[all …]
DHexagonMachineScheduler.cpp53 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
105 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
DHexagonInstrInfoV5.td607 (i32 (EXTRACT_SUBREG (i64 (CONVERT_df2d (f64 DoubleRegs:$src1))), subreg_loreg))>,
620 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
624 (CLRBIT_31 (f32 (EXTRACT_SUBREG DoubleRegs:$src1, subreg_hireg)), 31)>,
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td1140 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1155 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1161 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1282 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1290 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1297 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1300 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1306 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1313 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1316 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
[all …]
DX86InstrSSE.td252 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
254 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
257 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
259 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
262 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
264 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
540 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
544 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
600 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
605 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
[all …]
DX86InstrArithmetic.td1249 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
/external/llvm/include/llvm/Target/
DTargetOpcodes.h41 EXTRACT_SUBREG = 6, enumerator
DTarget.td702 def EXTRACT_SUBREG : Instruction {
/external/llvm/lib/Target/R600/
DSIInstructions.td1221 (EXTRACT_SUBREG addr_class:$addr, sub0),
1230 (EXTRACT_SUBREG addr_class:$addr, sub0),
1239 (EXTRACT_SUBREG addr_class:$addr, sub0),
1248 (EXTRACT_SUBREG addr_class:$addr, sub0),
1257 (EXTRACT_SUBREG addr_class:$addr, sub0),
1434 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG VReg_64:$ij, sub0),
1436 (EXTRACT_SUBREG VReg_64:$ij, sub1),
1471 (V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0),
1472 (EXTRACT_SUBREG VReg_128:$src, sub1),
1473 (EXTRACT_SUBREG VReg_128:$src, sub2),
[all …]
DAMDGPUInstructions.td178 (EXTRACT_SUBREG vec_class:$src, sub_reg)
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3995 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4001 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4007 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4022 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4029 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4044 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4051 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4095 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4103 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4112 (v2f32 (EXTRACT_SUBREG QPR:$src3,
[all …]
DARMISelDAGToDAG.cpp3165 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
3177 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp218 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp264 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
304 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
DScheduleDAGRRList.cpp1897 if (Opc == TargetOpcode::EXTRACT_SUBREG || in getNodePriority()
2117 if (Opc == TargetOpcode::EXTRACT_SUBREG || in unscheduledNode()
2146 if (POpc == TargetOpcode::EXTRACT_SUBREG || in unscheduledNode()
2588 if (Opc == TargetOpcode::EXTRACT_SUBREG || in canEnableCoalescing()
2960 if (SuccOpc == TargetOpcode::EXTRACT_SUBREG || in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp471 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
694 if (Opc == TargetOpcode::EXTRACT_SUBREG || in EmitMachineNode()
DSelectionDAG.cpp5411 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, in getTargetExtractSubreg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td294 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
299 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1135 (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
1210 (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit),
1211 (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1097 (SXTBxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1099 (SXTHxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1101 (SXTWxw (EXTRACT_SUBREG GPR64:$Rn, sub_32))>;
1774 (LSLVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1776 (LSRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1778 (ASRVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
1780 (RORVwww GPR32:$Rn, (EXTRACT_SUBREG GPR64:$Rm, sub_32))>;
4556 (BFIwwii (EXTRACT_SUBREG GPR64:$src, sub_32),
4557 (EXTRACT_SUBREG GPR64:$Rn, sub_32),
4569 def : Pat<(i32 (trunc (i64 GPR64:$val))), (EXTRACT_SUBREG GPR64:$val, sub_32)>;
[all …]
DAArch64ISelLowering.cpp969 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, in LowerFormalArguments()
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td294 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td921 (EXTRACT_SUBREG G8RC:$in, sub_32)>;