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1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
16 
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/Support/CallSite.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <vector>
26 
27 namespace llvm {
28 
29 class AliasAnalysis;
30 class AllocaInst;
31 class BasicBlock;
32 class BitCastInst;
33 class BranchInst;
34 class CallInst;
35 class DbgValueInst;
36 class ExtractElementInst;
37 class ExtractValueInst;
38 class FCmpInst;
39 class FPExtInst;
40 class FPToSIInst;
41 class FPToUIInst;
42 class FPTruncInst;
43 class Function;
44 class FunctionLoweringInfo;
45 class GetElementPtrInst;
46 class GCFunctionInfo;
47 class ICmpInst;
48 class IntToPtrInst;
49 class IndirectBrInst;
50 class InvokeInst;
51 class InsertElementInst;
52 class InsertValueInst;
53 class Instruction;
54 class LoadInst;
55 class MachineBasicBlock;
56 class MachineInstr;
57 class MachineRegisterInfo;
58 class MDNode;
59 class PHINode;
60 class PtrToIntInst;
61 class ReturnInst;
62 class SDDbgValue;
63 class SExtInst;
64 class SelectInst;
65 class ShuffleVectorInst;
66 class SIToFPInst;
67 class StoreInst;
68 class SwitchInst;
69 class DataLayout;
70 class TargetLibraryInfo;
71 class TargetLowering;
72 class TruncInst;
73 class UIToFPInst;
74 class UnreachableInst;
75 class VAArgInst;
76 class ZExtInst;
77 
78 //===----------------------------------------------------------------------===//
79 /// SelectionDAGBuilder - This is the common target-independent lowering
80 /// implementation that is parameterized by a TargetLowering object.
81 ///
82 class SelectionDAGBuilder {
83   /// CurDebugLoc - current file + line number.  Changes as we build the DAG.
84   DebugLoc CurDebugLoc;
85 
86   DenseMap<const Value*, SDValue> NodeMap;
87 
88   /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
89   /// to preserve debug information for incoming arguments.
90   DenseMap<const Value*, SDValue> UnusedArgNodeMap;
91 
92   /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
93   class DanglingDebugInfo {
94     const DbgValueInst* DI;
95     DebugLoc dl;
96     unsigned SDNodeOrder;
97   public:
DanglingDebugInfo()98     DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
DanglingDebugInfo(const DbgValueInst * di,DebugLoc DL,unsigned SDNO)99     DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
100       DI(di), dl(DL), SDNodeOrder(SDNO) { }
getDI()101     const DbgValueInst* getDI() { return DI; }
getdl()102     DebugLoc getdl() { return dl; }
getSDNodeOrder()103     unsigned getSDNodeOrder() { return SDNodeOrder; }
104   };
105 
106   /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
107   /// yet seen the referent.  We defer handling these until we do see it.
108   DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
109 
110 public:
111   /// PendingLoads - Loads are not emitted to the program immediately.  We bunch
112   /// them up and then emit token factor nodes when possible.  This allows us to
113   /// get simple disambiguation between loads without worrying about alias
114   /// analysis.
115   SmallVector<SDValue, 8> PendingLoads;
116 private:
117 
118   /// PendingExports - CopyToReg nodes that copy values to virtual registers
119   /// for export to other blocks need to be emitted before any terminator
120   /// instruction, but they have no other ordering requirements. We bunch them
121   /// up and the emit a single tokenfactor for them just before terminator
122   /// instructions.
123   SmallVector<SDValue, 8> PendingExports;
124 
125   /// SDNodeOrder - A unique monotonically increasing number used to order the
126   /// SDNodes we create.
127   unsigned SDNodeOrder;
128 
129   /// Case - A struct to record the Value for a switch case, and the
130   /// case's target basic block.
131   struct Case {
132     const Constant *Low;
133     const Constant *High;
134     MachineBasicBlock* BB;
135     uint32_t ExtraWeight;
136 
CaseCase137     Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
CaseCase138     Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
139          uint32_t extraweight) : Low(low), High(high), BB(bb),
140          ExtraWeight(extraweight) { }
141 
sizeCase142     APInt size() const {
143       const APInt &rHigh = cast<ConstantInt>(High)->getValue();
144       const APInt &rLow  = cast<ConstantInt>(Low)->getValue();
145       return (rHigh - rLow + 1ULL);
146     }
147   };
148 
149   struct CaseBits {
150     uint64_t Mask;
151     MachineBasicBlock* BB;
152     unsigned Bits;
153     uint32_t ExtraWeight;
154 
CaseBitsCaseBits155     CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
156              uint32_t Weight):
157       Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
158   };
159 
160   typedef std::vector<Case>           CaseVector;
161   typedef std::vector<CaseBits>       CaseBitsVector;
162   typedef CaseVector::iterator        CaseItr;
163   typedef std::pair<CaseItr, CaseItr> CaseRange;
164 
165   /// CaseRec - A struct with ctor used in lowering switches to a binary tree
166   /// of conditional branches.
167   struct CaseRec {
CaseRecCaseRec168     CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
169             CaseRange r) :
170     CaseBB(bb), LT(lt), GE(ge), Range(r) {}
171 
172     /// CaseBB - The MBB in which to emit the compare and branch
173     MachineBasicBlock *CaseBB;
174     /// LT, GE - If nonzero, we know the current case value must be less-than or
175     /// greater-than-or-equal-to these Constants.
176     const Constant *LT;
177     const Constant *GE;
178     /// Range - A pair of iterators representing the range of case values to be
179     /// processed at this point in the binary search tree.
180     CaseRange Range;
181   };
182 
183   typedef std::vector<CaseRec> CaseRecVector;
184 
185   struct CaseBitsCmp {
operatorCaseBitsCmp186     bool operator()(const CaseBits &C1, const CaseBits &C2) {
187       return C1.Bits > C2.Bits;
188     }
189   };
190 
191   size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
192 
193   /// CaseBlock - This structure is used to communicate between
194   /// SelectionDAGBuilder and SDISel for the code generation of additional basic
195   /// blocks needed by multi-case switch statements.
196   struct CaseBlock {
197     CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
198               const Value *cmpmiddle,
199               MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
200               MachineBasicBlock *me,
201               uint32_t trueweight = 0, uint32_t falseweight = 0)
CCCaseBlock202       : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
203         TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
204         TrueWeight(trueweight), FalseWeight(falseweight) { }
205 
206     // CC - the condition code to use for the case block's setcc node
207     ISD::CondCode CC;
208 
209     // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
210     // Emit by default LHS op RHS. MHS is used for range comparisons:
211     // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
212     const Value *CmpLHS, *CmpMHS, *CmpRHS;
213 
214     // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
215     MachineBasicBlock *TrueBB, *FalseBB;
216 
217     // ThisBB - the block into which to emit the code for the setcc and branches
218     MachineBasicBlock *ThisBB;
219 
220     // TrueWeight/FalseWeight - branch weights.
221     uint32_t TrueWeight, FalseWeight;
222   };
223 
224   struct JumpTable {
JumpTableJumpTable225     JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
226               MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
227 
228     /// Reg - the virtual register containing the index of the jump table entry
229     //. to jump to.
230     unsigned Reg;
231     /// JTI - the JumpTableIndex for this jump table in the function.
232     unsigned JTI;
233     /// MBB - the MBB into which to emit the code for the indirect jump.
234     MachineBasicBlock *MBB;
235     /// Default - the MBB of the default bb, which is a successor of the range
236     /// check MBB.  This is when updating PHI nodes in successors.
237     MachineBasicBlock *Default;
238   };
239   struct JumpTableHeader {
240     JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
241                     bool E = false):
FirstJumpTableHeader242       First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
243     APInt First;
244     APInt Last;
245     const Value *SValue;
246     MachineBasicBlock *HeaderBB;
247     bool Emitted;
248   };
249   typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
250 
251   struct BitTestCase {
BitTestCaseBitTestCase252     BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
253                 uint32_t Weight):
254       Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
255     uint64_t Mask;
256     MachineBasicBlock *ThisBB;
257     MachineBasicBlock *TargetBB;
258     uint32_t ExtraWeight;
259   };
260 
261   typedef SmallVector<BitTestCase, 3> BitTestInfo;
262 
263   struct BitTestBlock {
BitTestBlockBitTestBlock264     BitTestBlock(APInt F, APInt R, const Value* SV,
265                  unsigned Rg, MVT RgVT, bool E,
266                  MachineBasicBlock* P, MachineBasicBlock* D,
267                  const BitTestInfo& C):
268       First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
269       Parent(P), Default(D), Cases(C) { }
270     APInt First;
271     APInt Range;
272     const Value *SValue;
273     unsigned Reg;
274     MVT RegVT;
275     bool Emitted;
276     MachineBasicBlock *Parent;
277     MachineBasicBlock *Default;
278     BitTestInfo Cases;
279   };
280 
281 public:
282   // TLI - This is information that describes the available target features we
283   // need for lowering.  This indicates when operations are unavailable,
284   // implemented with a libcall, etc.
285   const TargetMachine &TM;
286   const TargetLowering &TLI;
287   SelectionDAG &DAG;
288   const DataLayout *TD;
289   AliasAnalysis *AA;
290   const TargetLibraryInfo *LibInfo;
291 
292   /// SwitchCases - Vector of CaseBlock structures used to communicate
293   /// SwitchInst code generation information.
294   std::vector<CaseBlock> SwitchCases;
295   /// JTCases - Vector of JumpTable structures used to communicate
296   /// SwitchInst code generation information.
297   std::vector<JumpTableBlock> JTCases;
298   /// BitTestCases - Vector of BitTestBlock structures used to communicate
299   /// SwitchInst code generation information.
300   std::vector<BitTestBlock> BitTestCases;
301 
302   // Emit PHI-node-operand constants only once even if used by multiple
303   // PHI nodes.
304   DenseMap<const Constant *, unsigned> ConstantsOut;
305 
306   /// FuncInfo - Information about the function as a whole.
307   ///
308   FunctionLoweringInfo &FuncInfo;
309 
310   /// OptLevel - What optimization level we're generating code for.
311   ///
312   CodeGenOpt::Level OptLevel;
313 
314   /// GFI - Garbage collection metadata for the function.
315   GCFunctionInfo *GFI;
316 
317   /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
318   DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
319 
320   /// HasTailCall - This is set to true if a call in the current
321   /// block has been translated as a tail call. In this case,
322   /// no subsequent DAG nodes should be created.
323   ///
324   bool HasTailCall;
325 
326   LLVMContext *Context;
327 
SelectionDAGBuilder(SelectionDAG & dag,FunctionLoweringInfo & funcinfo,CodeGenOpt::Level ol)328   SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
329                       CodeGenOpt::Level ol)
330     : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
331       DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
332       HasTailCall(false) {
333   }
334 
335   void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
336             const TargetLibraryInfo *li);
337 
338   /// clear - Clear out the current SelectionDAG and the associated
339   /// state and prepare this SelectionDAGBuilder object to be used
340   /// for a new block. This doesn't clear out information about
341   /// additional blocks that are needed to complete switch lowering
342   /// or PHI node updating; that information is cleared out as it is
343   /// consumed.
344   void clear();
345 
346   /// clearDanglingDebugInfo - Clear the dangling debug information
347   /// map. This function is separated from the clear so that debug
348   /// information that is dangling in a basic block can be properly
349   /// resolved in a different basic block. This allows the
350   /// SelectionDAG to resolve dangling debug information attached
351   /// to PHI nodes.
352   void clearDanglingDebugInfo();
353 
354   /// getRoot - Return the current virtual root of the Selection DAG,
355   /// flushing any PendingLoad items. This must be done before emitting
356   /// a store or any other node that may need to be ordered after any
357   /// prior load instructions.
358   ///
359   SDValue getRoot();
360 
361   /// getControlRoot - Similar to getRoot, but instead of flushing all the
362   /// PendingLoad items, flush all the PendingExports items. It is necessary
363   /// to do this before emitting a terminator instruction.
364   ///
365   SDValue getControlRoot();
366 
getCurDebugLoc()367   DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
368 
getSDNodeOrder()369   unsigned getSDNodeOrder() const { return SDNodeOrder; }
370 
371   void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
372 
373   /// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
374   /// from how the code appeared in the source. The ordering is used by the
375   /// scheduler to effectively turn off scheduling.
376   void AssignOrderingToNode(const SDNode *Node);
377 
378   void visit(const Instruction &I);
379 
380   void visit(unsigned Opcode, const User &I);
381 
382   // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
383   // generate the debug data structures now that we've seen its definition.
384   void resolveDanglingDebugInfo(const Value *V, SDValue Val);
385   SDValue getValue(const Value *V);
386   SDValue getNonRegisterValue(const Value *V);
387   SDValue getValueImpl(const Value *V);
388 
setValue(const Value * V,SDValue NewN)389   void setValue(const Value *V, SDValue NewN) {
390     SDValue &N = NodeMap[V];
391     assert(N.getNode() == 0 && "Already set a value for this node!");
392     N = NewN;
393   }
394 
setUnusedArgValue(const Value * V,SDValue NewN)395   void setUnusedArgValue(const Value *V, SDValue NewN) {
396     SDValue &N = UnusedArgNodeMap[V];
397     assert(N.getNode() == 0 && "Already set a value for this node!");
398     N = NewN;
399   }
400 
401   void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
402                             MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
403                             MachineBasicBlock *SwitchBB, unsigned Opc);
404   void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
405                                     MachineBasicBlock *FBB,
406                                     MachineBasicBlock *CurBB,
407                                     MachineBasicBlock *SwitchBB);
408   bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
409   bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
410   void CopyToExportRegsIfNeeded(const Value *V);
411   void ExportFromCurrentBlock(const Value *V);
412   void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
413                    MachineBasicBlock *LandingPad = NULL);
414 
415   /// UpdateSplitBlock - When an MBB was split during scheduling, update the
416   /// references that ned to refer to the last resulting block.
417   void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
418 
419 private:
420   // Terminator instructions.
421   void visitRet(const ReturnInst &I);
422   void visitBr(const BranchInst &I);
423   void visitSwitch(const SwitchInst &I);
424   void visitIndirectBr(const IndirectBrInst &I);
visitUnreachable(const UnreachableInst & I)425   void visitUnreachable(const UnreachableInst &I) { /* noop */ }
426 
427   // Helpers for visitSwitch
428   bool handleSmallSwitchRange(CaseRec& CR,
429                               CaseRecVector& WorkList,
430                               const Value* SV,
431                               MachineBasicBlock* Default,
432                               MachineBasicBlock *SwitchBB);
433   bool handleJTSwitchCase(CaseRec& CR,
434                           CaseRecVector& WorkList,
435                           const Value* SV,
436                           MachineBasicBlock* Default,
437                           MachineBasicBlock *SwitchBB);
438   bool handleBTSplitSwitchCase(CaseRec& CR,
439                                CaseRecVector& WorkList,
440                                const Value* SV,
441                                MachineBasicBlock* Default,
442                                MachineBasicBlock *SwitchBB);
443   bool handleBitTestsSwitchCase(CaseRec& CR,
444                                 CaseRecVector& WorkList,
445                                 const Value* SV,
446                                 MachineBasicBlock* Default,
447                                 MachineBasicBlock *SwitchBB);
448 
449   uint32_t getEdgeWeight(const MachineBasicBlock *Src,
450                          const MachineBasicBlock *Dst) const;
451   void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
452                               uint32_t Weight = 0);
453 public:
454   void visitSwitchCase(CaseBlock &CB,
455                        MachineBasicBlock *SwitchBB);
456   void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
457   void visitBitTestCase(BitTestBlock &BB,
458                         MachineBasicBlock* NextMBB,
459                         uint32_t BranchWeightToNext,
460                         unsigned Reg,
461                         BitTestCase &B,
462                         MachineBasicBlock *SwitchBB);
463   void visitJumpTable(JumpTable &JT);
464   void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
465                             MachineBasicBlock *SwitchBB);
466 
467 private:
468   // These all get lowered before this pass.
469   void visitInvoke(const InvokeInst &I);
470   void visitResume(const ResumeInst &I);
471 
472   void visitBinary(const User &I, unsigned OpCode);
473   void visitShift(const User &I, unsigned Opcode);
visitAdd(const User & I)474   void visitAdd(const User &I)  { visitBinary(I, ISD::ADD); }
visitFAdd(const User & I)475   void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
visitSub(const User & I)476   void visitSub(const User &I)  { visitBinary(I, ISD::SUB); }
477   void visitFSub(const User &I);
visitMul(const User & I)478   void visitMul(const User &I)  { visitBinary(I, ISD::MUL); }
visitFMul(const User & I)479   void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
visitURem(const User & I)480   void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
visitSRem(const User & I)481   void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
visitFRem(const User & I)482   void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
visitUDiv(const User & I)483   void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
484   void visitSDiv(const User &I);
visitFDiv(const User & I)485   void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
visitAnd(const User & I)486   void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
visitOr(const User & I)487   void visitOr  (const User &I) { visitBinary(I, ISD::OR); }
visitXor(const User & I)488   void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
visitShl(const User & I)489   void visitShl (const User &I) { visitShift(I, ISD::SHL); }
visitLShr(const User & I)490   void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
visitAShr(const User & I)491   void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
492   void visitICmp(const User &I);
493   void visitFCmp(const User &I);
494   // Visit the conversion instructions
495   void visitTrunc(const User &I);
496   void visitZExt(const User &I);
497   void visitSExt(const User &I);
498   void visitFPTrunc(const User &I);
499   void visitFPExt(const User &I);
500   void visitFPToUI(const User &I);
501   void visitFPToSI(const User &I);
502   void visitUIToFP(const User &I);
503   void visitSIToFP(const User &I);
504   void visitPtrToInt(const User &I);
505   void visitIntToPtr(const User &I);
506   void visitBitCast(const User &I);
507 
508   void visitExtractElement(const User &I);
509   void visitInsertElement(const User &I);
510   void visitShuffleVector(const User &I);
511 
512   void visitExtractValue(const ExtractValueInst &I);
513   void visitInsertValue(const InsertValueInst &I);
514   void visitLandingPad(const LandingPadInst &I);
515 
516   void visitGetElementPtr(const User &I);
517   void visitSelect(const User &I);
518 
519   void visitAlloca(const AllocaInst &I);
520   void visitLoad(const LoadInst &I);
521   void visitStore(const StoreInst &I);
522   void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
523   void visitAtomicRMW(const AtomicRMWInst &I);
524   void visitFence(const FenceInst &I);
525   void visitPHI(const PHINode &I);
526   void visitCall(const CallInst &I);
527   bool visitMemCmpCall(const CallInst &I);
528   bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
529   void visitAtomicLoad(const LoadInst &I);
530   void visitAtomicStore(const StoreInst &I);
531 
532   void visitInlineAsm(ImmutableCallSite CS);
533   const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
534   void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
535 
536   void visitVAStart(const CallInst &I);
537   void visitVAArg(const VAArgInst &I);
538   void visitVAEnd(const CallInst &I);
539   void visitVACopy(const CallInst &I);
540 
visitUserOp1(const Instruction & I)541   void visitUserOp1(const Instruction &I) {
542     llvm_unreachable("UserOp1 should not exist at instruction selection time!");
543   }
visitUserOp2(const Instruction & I)544   void visitUserOp2(const Instruction &I) {
545     llvm_unreachable("UserOp2 should not exist at instruction selection time!");
546   }
547 
548   void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
549 
550   /// EmitFuncArgumentDbgValue - If V is an function argument then create
551   /// corresponding DBG_VALUE machine instruction for it now. At the end of
552   /// instruction selection, they will be inserted to the entry BB.
553   bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
554                                 int64_t Offset, const SDValue &N);
555 };
556 
557 } // end namespace llvm
558 
559 #endif
560