1//===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//==-----------------------------------------------------------------------===// 9// 10// This file describes the AMDIL instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13// AMDIL Instruction Predicate Definitions 14// Predicate that is set to true if the hardware supports double precision 15// divide 16def HasHWDDiv : Predicate<"Subtarget.device()" 17 "->getGeneration() > AMDGPUDeviceInfo::HD4XXX && " 18 "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">; 19 20// Predicate that is set to true if the hardware supports double, but not double 21// precision divide in hardware 22def HasSWDDiv : Predicate<"Subtarget.device()" 23 "->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&" 24 "Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">; 25 26// Predicate that is set to true if the hardware support 24bit signed 27// math ops. Otherwise a software expansion to 32bit math ops is used instead. 28def HasHWSign24Bit : Predicate<"Subtarget.device()" 29 "->getGeneration() > AMDGPUDeviceInfo::HD5XXX">; 30 31// Predicate that is set to true if 64bit operations are supported or not 32def HasHW64Bit : Predicate<"Subtarget.device()" 33 "->usesHardware(AMDGPUDeviceInfo::LongOps)">; 34def HasSW64Bit : Predicate<"Subtarget.device()" 35 "->usesSoftware(AMDGPUDeviceInfo::LongOps)">; 36 37// Predicate that is set to true if the timer register is supported 38def HasTmrRegister : Predicate<"Subtarget.device()" 39 "->isSupported(AMDGPUDeviceInfo::TmrReg)">; 40// Predicate that is true if we are at least evergreen series 41def HasDeviceIDInst : Predicate<"Subtarget.device()" 42 "->getGeneration() >= AMDGPUDeviceInfo::HD5XXX">; 43 44// Predicate that is true if we have region address space. 45def hasRegionAS : Predicate<"Subtarget.device()" 46 "->usesHardware(AMDGPUDeviceInfo::RegionMem)">; 47 48// Predicate that is false if we don't have region address space. 49def noRegionAS : Predicate<"!Subtarget.device()" 50 "->isSupported(AMDGPUDeviceInfo::RegionMem)">; 51 52 53// Predicate that is set to true if 64bit Mul is supported in the IL or not 54def HasHW64Mul : Predicate<"Subtarget.calVersion()" 55 ">= CAL_VERSION_SC_139" 56 "&& Subtarget.device()" 57 "->getGeneration() >=" 58 "AMDGPUDeviceInfo::HD5XXX">; 59def HasSW64Mul : Predicate<"Subtarget.calVersion()" 60 "< CAL_VERSION_SC_139">; 61// Predicate that is set to true if 64bit Div/Mod is supported in the IL or not 62def HasHW64DivMod : Predicate<"Subtarget.device()" 63 "->usesHardware(AMDGPUDeviceInfo::HW64BitDivMod)">; 64def HasSW64DivMod : Predicate<"Subtarget.device()" 65 "->usesSoftware(AMDGPUDeviceInfo::HW64BitDivMod)">; 66 67// Predicate that is set to true if 64bit pointer are used. 68def Has64BitPtr : Predicate<"Subtarget.is64bit()">; 69def Has32BitPtr : Predicate<"!Subtarget.is64bit()">; 70//===--------------------------------------------------------------------===// 71// Custom Operands 72//===--------------------------------------------------------------------===// 73def brtarget : Operand<OtherVT>; 74 75//===--------------------------------------------------------------------===// 76// Custom Selection DAG Type Profiles 77//===--------------------------------------------------------------------===// 78//===----------------------------------------------------------------------===// 79// Generic Profile Types 80//===----------------------------------------------------------------------===// 81 82def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [ 83 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 84 ]>; 85def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [ 86 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3> 87 ]>; 88def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [ 89 SDTCisEltOfVec<1, 0> 90 ]>; 91 92//===----------------------------------------------------------------------===// 93// Flow Control Profile Types 94//===----------------------------------------------------------------------===// 95// Branch instruction where second and third are basic blocks 96def SDTIL_BRCond : SDTypeProfile<0, 2, [ 97 SDTCisVT<0, OtherVT> 98 ]>; 99 100//===--------------------------------------------------------------------===// 101// Custom Selection DAG Nodes 102//===--------------------------------------------------------------------===// 103//===----------------------------------------------------------------------===// 104// Flow Control DAG Nodes 105//===----------------------------------------------------------------------===// 106def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; 107 108//===----------------------------------------------------------------------===// 109// Call/Return DAG Nodes 110//===----------------------------------------------------------------------===// 111def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone, 112 [SDNPHasChain, SDNPOptInGlue]>; 113 114//===--------------------------------------------------------------------===// 115// Instructions 116//===--------------------------------------------------------------------===// 117// Floating point math functions 118def IL_div_inf : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>; 119 120//===----------------------------------------------------------------------===// 121// Integer functions 122//===----------------------------------------------------------------------===// 123def IL_umul : SDNode<"AMDGPUISD::UMUL" , SDTIntBinOp, 124 [SDNPCommutative, SDNPAssociative]>; 125 126//===--------------------------------------------------------------------===// 127// Custom Pattern DAG Nodes 128//===--------------------------------------------------------------------===// 129def global_store : PatFrag<(ops node:$val, node:$ptr), 130 (store node:$val, node:$ptr), [{ 131 return isGlobalStore(dyn_cast<StoreSDNode>(N)); 132}]>; 133 134//===----------------------------------------------------------------------===// 135// Load pattern fragments 136//===----------------------------------------------------------------------===// 137// Global address space loads 138def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 139 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 140}]>; 141// Constant address space loads 142def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 143 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 144}]>; 145 146//===----------------------------------------------------------------------===// 147// Complex addressing mode patterns 148//===----------------------------------------------------------------------===// 149def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; 150def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>; 151def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>; 152def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>; 153 154//===----------------------------------------------------------------------===// 155// Instruction format classes 156//===----------------------------------------------------------------------===// 157class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern> 158: Instruction { 159 160 let Namespace = "AMDGPU"; 161 dag OutOperandList = outs; 162 dag InOperandList = ins; 163 let Pattern = pattern; 164 let AsmString = !strconcat(asmstr, "\n"); 165 let isPseudo = 1; 166 let Itinerary = NullALU; 167 bit hasIEEEFlag = 0; 168 bit hasZeroOpFlag = 0; 169 let mayLoad = 0; 170 let mayStore = 0; 171 let hasSideEffects = 0; 172} 173 174//===--------------------------------------------------------------------===// 175// Multiclass Instruction formats 176//===--------------------------------------------------------------------===// 177// Multiclass that handles branch instructions 178multiclass BranchConditional<SDNode Op> { 179 def _i32 : ILFormat<(outs), 180 (ins brtarget:$target, GPRI32:$src0), 181 "; i32 Pseudo branch instruction", 182 [(Op bb:$target, GPRI32:$src0)]>; 183 def _f32 : ILFormat<(outs), 184 (ins brtarget:$target, GPRF32:$src0), 185 "; f32 Pseudo branch instruction", 186 [(Op bb:$target, GPRF32:$src0)]>; 187} 188 189// Only scalar types should generate flow control 190multiclass BranchInstr<string name> { 191 def _i32 : ILFormat<(outs), (ins GPRI32:$src), 192 !strconcat(name, " $src"), []>; 193 def _f32 : ILFormat<(outs), (ins GPRF32:$src), 194 !strconcat(name, " $src"), []>; 195} 196// Only scalar types should generate flow control 197multiclass BranchInstr2<string name> { 198 def _i32 : ILFormat<(outs), (ins GPRI32:$src0, GPRI32:$src1), 199 !strconcat(name, " $src0, $src1"), []>; 200 def _f32 : ILFormat<(outs), (ins GPRF32:$src0, GPRF32:$src1), 201 !strconcat(name, " $src0, $src1"), []>; 202} 203 204//===--------------------------------------------------------------------===// 205// Intrinsics support 206//===--------------------------------------------------------------------===// 207include "AMDILIntrinsics.td" 208