1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for R600InstrInfo 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef R600INSTRUCTIONINFO_H_ 16 #define R600INSTRUCTIONINFO_H_ 17 18 #include "AMDGPUInstrInfo.h" 19 #include "AMDIL.h" 20 #include "R600Defines.h" 21 #include "R600RegisterInfo.h" 22 #include <map> 23 24 namespace llvm { 25 26 class AMDGPUTargetMachine; 27 class DFAPacketizer; 28 class ScheduleDAG; 29 class MachineFunction; 30 class MachineInstr; 31 class MachineInstrBuilder; 32 33 class R600InstrInfo : public AMDGPUInstrInfo { 34 private: 35 const R600RegisterInfo RI; 36 37 int getBranchInstr(const MachineOperand &op) const; 38 39 public: 40 explicit R600InstrInfo(AMDGPUTargetMachine &tm); 41 42 const R600RegisterInfo &getRegisterInfo() const; 43 virtual void copyPhysReg(MachineBasicBlock &MBB, 44 MachineBasicBlock::iterator MI, DebugLoc DL, 45 unsigned DestReg, unsigned SrcReg, 46 bool KillSrc) const; 47 48 bool isTrig(const MachineInstr &MI) const; 49 bool isPlaceHolderOpcode(unsigned opcode) const; 50 bool isReductionOp(unsigned opcode) const; 51 bool isCubeOp(unsigned opcode) const; 52 53 /// \returns true if this \p Opcode represents an ALU instruction. 54 bool isALUInstr(unsigned Opcode) const; 55 56 bool fitsConstReadLimitations(const std::vector<unsigned>&) const; 57 bool canBundle(const std::vector<MachineInstr *> &) const; 58 59 /// \breif Vector instructions are instructions that must fill all 60 /// instruction slots within an instruction group. 61 bool isVector(const MachineInstr &MI) const; 62 63 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 64 int64_t Imm) const; 65 66 virtual unsigned getIEQOpcode() const; 67 virtual bool isMov(unsigned Opcode) const; 68 69 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 70 const ScheduleDAG *DAG) const; 71 72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 73 74 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 75 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 76 77 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; 78 79 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 80 81 bool isPredicated(const MachineInstr *MI) const; 82 83 bool isPredicable(MachineInstr *MI) const; 84 85 bool 86 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 87 const BranchProbability &Probability) const; 88 89 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 90 unsigned ExtraPredCycles, 91 const BranchProbability &Probability) const ; 92 93 bool 94 isProfitableToIfCvt(MachineBasicBlock &TMBB, 95 unsigned NumTCycles, unsigned ExtraTCycles, 96 MachineBasicBlock &FMBB, 97 unsigned NumFCycles, unsigned ExtraFCycles, 98 const BranchProbability &Probability) const; 99 100 bool DefinesPredicate(MachineInstr *MI, 101 std::vector<MachineOperand> &Pred) const; 102 103 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 104 const SmallVectorImpl<MachineOperand> &Pred2) const; 105 106 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 107 MachineBasicBlock &FMBB) const; 108 109 bool PredicateInstruction(MachineInstr *MI, 110 const SmallVectorImpl<MachineOperand> &Pred) const; 111 112 unsigned int getInstrLatency(const InstrItineraryData *ItinData, 113 const MachineInstr *MI, 114 unsigned *PredCost = 0) const; 115 getInstrLatency(const InstrItineraryData * ItinData,SDNode * Node)116 virtual int getInstrLatency(const InstrItineraryData *ItinData, 117 SDNode *Node) const { return 1;} 118 119 /// \returns a list of all the registers that may be accesed using indirect 120 /// addressing. 121 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const; 122 123 virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 124 125 virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 126 127 128 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 129 unsigned Channel) const; 130 131 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 132 unsigned SourceReg) const; 133 134 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; 135 136 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 137 MachineBasicBlock::iterator I, 138 unsigned ValueReg, unsigned Address, 139 unsigned OffsetReg) const; 140 141 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 142 MachineBasicBlock::iterator I, 143 unsigned ValueReg, unsigned Address, 144 unsigned OffsetReg) const; 145 146 virtual const TargetRegisterClass *getSuperIndirectRegClass() const; 147 148 149 ///buildDefaultInstruction - This function returns a MachineInstr with 150 /// all the instruction modifiers initialized to their default values. 151 /// You can use this function to avoid manually specifying each instruction 152 /// modifier operand when building a new instruction. 153 /// 154 /// \returns a MachineInstr with all the instruction modifiers initialized 155 /// to their default values. 156 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, 157 MachineBasicBlock::iterator I, 158 unsigned Opcode, 159 unsigned DstReg, 160 unsigned Src0Reg, 161 unsigned Src1Reg = 0) const; 162 163 MachineInstr *buildMovImm(MachineBasicBlock &BB, 164 MachineBasicBlock::iterator I, 165 unsigned DstReg, 166 uint64_t Imm) const; 167 168 /// \brief Get the index of Op in the MachineInstr. 169 /// 170 /// \returns -1 if the Instruction does not contain the specified \p Op. 171 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const; 172 173 /// \brief Get the index of \p Op for the given Opcode. 174 /// 175 /// \returns -1 if the Instruction does not contain the specified \p Op. 176 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const; 177 178 /// \brief Helper function for setting instruction flag values. 179 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const; 180 181 /// \returns true if this instruction has an operand for storing target flags. 182 bool hasFlagOperand(const MachineInstr &MI) const; 183 184 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand. 185 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 186 187 ///\brief Determine if the specified \p Flag is set on this \p Operand. 188 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 189 190 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2) 191 /// \param Flag The flag being set. 192 /// 193 /// \returns the operand containing the flags for this instruction. 194 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0, 195 unsigned Flag = 0) const; 196 197 /// \brief Clear the specified flag on the instruction. 198 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 199 }; 200 201 } // End llvm namespace 202 203 #endif // R600INSTRINFO_H_ 204