1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s 2 3%myStruct = type { i64 , i8, i32 } 4 5@var8 = global i8 0 6@var32 = global i32 0 7@var64 = global i64 0 8@var128 = global i128 0 9@varfloat = global float 0.0 10@vardouble = global double 0.0 11@varstruct = global %myStruct zeroinitializer 12 13define void @take_i8s(i8 %val1, i8 %val2) { 14; CHECK: take_i8s: 15 store i8 %val2, i8* @var8 16 ; Not using w1 may be technically allowed, but it would indicate a 17 ; problem in itself. 18; CHECK: strb w1, [{{x[0-9]+}}, #:lo12:var8] 19 ret void 20} 21 22define void @add_floats(float %val1, float %val2) { 23; CHECK: add_floats: 24 %newval = fadd float %val1, %val2 25; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1 26 store float %newval, float* @varfloat 27; CHECK: str [[ADDRES]], [{{x[0-9]+}}, #:lo12:varfloat] 28 ret void 29} 30 31; byval pointers should be allocated to the stack and copied as if 32; with memcpy. 33define void @take_struct(%myStruct* byval %structval) { 34; CHECK: take_struct: 35 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 36 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 37 38 %val0 = load i32* %addr0 39 ; Some weird move means x0 is used for one access 40; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] 41 store i32 %val0, i32* @var32 42; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] 43 44 %val1 = load i64* %addr1 45; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] 46 store i64 %val1, i64* @var64 47; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] 48 49 ret void 50} 51 52; %structval should be at sp + 16 53define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { 54; CHECK: check_byval_align: 55 56 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 57 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 58 59 %val0 = load i32* %addr0 60 ; Some weird move means x0 is used for one access 61; CHECK: add x[[STRUCTVAL_ADDR:[0-9]+]], sp, #16 62; CHECK: ldr [[REG32:w[0-9]+]], [x[[STRUCTVAL_ADDR]], #12] 63 store i32 %val0, i32* @var32 64; CHECK: str [[REG32]], [{{x[0-9]+}}, #:lo12:var32] 65 66 %val1 = load i64* %addr1 67; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] 68 store i64 %val1, i64* @var64 69; CHECK: str [[REG64]], [{{x[0-9]+}}, #:lo12:var64] 70 71 ret void 72} 73 74define i32 @return_int() { 75; CHECK: return_int: 76 %val = load i32* @var32 77 ret i32 %val 78; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32] 79 ; Make sure epilogue follows 80; CHECK-NEXT: ret 81} 82 83define double @return_double() { 84; CHECK: return_double: 85 ret double 3.14 86; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI 87} 88 89; This is the kind of IR clang will produce for returning a struct 90; small enough to go into registers. Not all that pretty, but it 91; works. 92define [2 x i64] @return_struct() { 93; CHECK: return_struct: 94 %addr = bitcast %myStruct* @varstruct to [2 x i64]* 95 %val = load [2 x i64]* %addr 96 ret [2 x i64] %val 97; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:varstruct] 98 ; Odd register regex below disallows x0 which we want to be live now. 99; CHECK: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, #:lo12:varstruct 100; CHECK-NEXT: ldr x1, [{{x[1-9][0-9]*}}, #8] 101 ; Make sure epilogue immediately follows 102; CHECK-NEXT: ret 103} 104 105; Large structs are passed by reference (storage allocated by caller 106; to preserve value semantics) in x8. Strictly this only applies to 107; structs larger than 16 bytes, but C semantics can still be provided 108; if LLVM does it to %myStruct too. So this is the simplest check 109define void @return_large_struct(%myStruct* sret %retval) { 110; CHECK: return_large_struct: 111 %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0 112 %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1 113 %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2 114 115 store i64 42, i64* %addr0 116 store i8 2, i8* %addr1 117 store i32 9, i32* %addr2 118; CHECK: str {{x[0-9]+}}, [x8] 119; CHECK: strb {{w[0-9]+}}, [x8, #8] 120; CHECK: str {{w[0-9]+}}, [x8, #12] 121 122 ret void 123} 124 125; This struct is just too far along to go into registers: (only x7 is 126; available, but it needs two). Also make sure that %stacked doesn't 127; sneak into x7 behind. 128define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, 129 i32* %var6, %myStruct* byval %struct, i32* byval %stacked, 130 double %notstacked) { 131; CHECK: struct_on_stack: 132 %addr = getelementptr %myStruct* %struct, i64 0, i32 0 133 %val64 = load i64* %addr 134 store i64 %val64, i64* @var64 135 ; Currently nothing on local stack, so struct should be at sp 136; CHECK: ldr [[VAL64:x[0-9]+]], [sp] 137; CHECK: str [[VAL64]], [{{x[0-9]+}}, #:lo12:var64] 138 139 store double %notstacked, double* @vardouble 140; CHECK-NOT: ldr d0 141; CHECK: str d0, [{{x[0-9]+}}, #:lo12:vardouble 142 143 %retval = load i32* %stacked 144 ret i32 %retval 145; CHECK: ldr w0, [sp, #16] 146} 147 148define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, 149 float %var4, float %var5, float %var6, float %var7, 150 float %var8) { 151; CHECK: stacked_fpu: 152 store float %var8, float* @varfloat 153 ; Beware as above: the offset would be different on big-endian 154 ; machines if the first ldr were changed to use s-registers. 155; CHECK: ldr d[[VALFLOAT:[0-9]+]], [sp] 156; CHECK: str s[[VALFLOAT]], [{{x[0-9]+}}, #:lo12:varfloat] 157 158 ret void 159} 160 161; 128-bit integer types should be passed in xEVEN, xODD rather than 162; the reverse. In this case x2 and x3. Nothing should use x1. 163define i32 @check_i128_regalign(i32 %val0, i128 %val1, i32 %val2) { 164; CHECK: check_i128_regalign 165 store i128 %val1, i128* @var128 166; CHECK: str x2, [{{x[0-9]+}}, #:lo12:var128] 167; CHECK: str x3, [{{x[0-9]+}}, #8] 168 169 ret i32 %val2 170; CHECK: mov x0, x4 171} 172 173define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, 174 i32 %val4, i32 %val5, i32 %val6, i32 %val7, 175 i32 %stack1, i128 %stack2) { 176; CHECK: check_i128_stackalign 177 store i128 %stack2, i128* @var128 178 ; Nothing local on stack in current codegen, so first stack is 16 away 179; CHECK: ldr {{x[0-9]+}}, [sp, #16] 180 ; Important point is that we address sp+24 for second dword 181; CHECK: add [[REG:x[0-9]+]], sp, #16 182; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8] 183 ret void 184} 185 186declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) 187 188define i32 @test_extern() { 189; CHECK: test_extern: 190 call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0) 191; CHECK: bl memcpy 192 ret i32 0 193} 194