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1; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
2
3define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
4entry:
5; CHECK: daddu
6  %add = add nsw i64 %a1, %a0
7  ret i64 %add
8}
9
10define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
11entry:
12; CHECK: dsubu
13  %sub = sub nsw i64 %a0, %a1
14  ret i64 %sub
15}
16
17define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
18entry:
19; CHECK: and
20  %and = and i64 %a1, %a0
21  ret i64 %and
22}
23
24define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
25entry:
26; CHECK: or
27  %or = or i64 %a1, %a0
28  ret i64 %or
29}
30
31define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
32entry:
33; CHECK: xor
34  %xor = xor i64 %a1, %a0
35  ret i64 %xor
36}
37
38define i64 @f7(i64 %a0) nounwind readnone {
39entry:
40; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
41  %add = add nsw i64 %a0, 20
42  ret i64 %add
43}
44
45define i64 @f8(i64 %a0) nounwind readnone {
46entry:
47; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
48  %sub = add nsw i64 %a0, -20
49  ret i64 %sub
50}
51
52define i64 @f9(i64 %a0) nounwind readnone {
53entry:
54; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
55  %and = and i64 %a0, 20
56  ret i64 %and
57}
58
59define i64 @f10(i64 %a0) nounwind readnone {
60entry:
61; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
62  %or = or i64 %a0, 20
63  ret i64 %or
64}
65
66define i64 @f11(i64 %a0) nounwind readnone {
67entry:
68; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
69  %xor = xor i64 %a0, 20
70  ret i64 %xor
71}
72
73define i64 @f12(i64 %a, i64 %b) nounwind readnone {
74entry:
75; CHECK: mult
76  %mul = mul nsw i64 %b, %a
77  ret i64 %mul
78}
79
80define i64 @f13(i64 %a, i64 %b) nounwind readnone {
81entry:
82; CHECK: mult
83  %mul = mul i64 %b, %a
84  ret i64 %mul
85}
86
87define i64 @f14(i64 %a, i64 %b) nounwind readnone {
88entry:
89; CHECK: ddiv $zero
90; CHECK: mflo
91  %div = sdiv i64 %a, %b
92  ret i64 %div
93}
94
95define i64 @f15(i64 %a, i64 %b) nounwind readnone {
96entry:
97; CHECK: ddivu $zero
98; CHECK: mflo
99  %div = udiv i64 %a, %b
100  ret i64 %div
101}
102
103define i64 @f16(i64 %a, i64 %b) nounwind readnone {
104entry:
105; CHECK: ddiv $zero
106; CHECK: mfhi
107  %rem = srem i64 %a, %b
108  ret i64 %rem
109}
110
111define i64 @f17(i64 %a, i64 %b) nounwind readnone {
112entry:
113; CHECK: ddivu $zero
114; CHECK: mfhi
115  %rem = urem i64 %a, %b
116  ret i64 %rem
117}
118
119declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
120
121define i64 @f18(i64 %X) nounwind readnone {
122entry:
123; CHECK: dclz $2, $4
124  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
125  ret i64 %tmp1
126}
127
128define i64 @f19(i64 %X) nounwind readnone {
129entry:
130; CHECK: dclo $2, $4
131  %neg = xor i64 %X, -1
132  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
133  ret i64 %tmp1
134}
135
136define i64 @f20(i64 %a, i64 %b) nounwind readnone {
137entry:
138; CHECK: nor
139  %or = or i64 %b, %a
140  %neg = xor i64 %or, -1
141  ret i64 %neg
142}
143
144