1; RUN: llc -O0 -mcpu=pwr7 < %s | FileCheck %s 2 3target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 4target triple = "powerpc64-unknown-linux-gnu" 5 6define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { 7 %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] 8 %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] 9 store <4 x i32> %tmp4, <4 x i32>* %P1 10 %tmp7 = load <4 x i32>* %P2 ; <<4 x i32>> [#uses=1] 11 %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 12 store <4 x i32> %tmp9, <4 x i32>* %P2 13 %tmp.upgrd.1 = load <4 x float>* %P3 ; <<4 x float>> [#uses=1] 14 %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1] 15 %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 16 %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] 17 store <4 x float> %tmp13, <4 x float>* %P3 18 ret void 19 20; CHECK: test1: 21; CHECK-NOT: CPI 22} 23 24define <4 x i32> @test_30() nounwind { 25 ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > 26 27; CHECK: test_30: 28; CHECK: vspltisw 29; CHECK-NEXT: vadduwm 30; CHECK-NEXT: blr 31} 32 33define <4 x i32> @test_29() nounwind { 34 ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > 35 36; CHECK: test_29: 37; CHECK: vspltisw 38; CHECK-NEXT: vspltisw 39; CHECK-NEXT: vsubuwm 40; CHECK-NEXT: blr 41} 42 43define <8 x i16> @test_n30() nounwind { 44 ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > 45 46; CHECK: test_n30: 47; CHECK: vspltish 48; CHECK-NEXT: vadduhm 49; CHECK-NEXT: blr 50} 51 52define <16 x i8> @test_n104() nounwind { 53 ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > 54 55; CHECK: test_n104: 56; CHECK: vspltisb 57; CHECK-NEXT: vslb 58; CHECK-NEXT: blr 59} 60 61define <4 x i32> @test_vsldoi() nounwind { 62 ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > 63 64; CHECK: test_vsldoi: 65; CHECK: vspltisw 66; CHECK-NEXT: vsldoi 67; CHECK-NEXT: blr 68} 69 70define <8 x i16> @test_vsldoi_65023() nounwind { 71 ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > 72 73; CHECK: test_vsldoi_65023: 74; CHECK: vspltish 75; CHECK-NEXT: vsldoi 76; CHECK-NEXT: blr 77} 78 79define <4 x i32> @test_rol() nounwind { 80 ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > 81 82; CHECK: test_rol: 83; CHECK: vspltisw 84; CHECK-NEXT: vrlw 85; CHECK-NEXT: blr 86} 87