1// RUN: llvm-tblgen %s | grep '\[(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))\]' | count 1 2// RUN: llvm-tblgen %s | grep '\[(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))\]' | count 1 3 4class ValueType<int size, int value> { 5 int Size = size; 6 int Value = value; 7} 8 9def v2i64 : ValueType<128, 22>; // 2 x i64 vector value 10def v2f64 : ValueType<128, 28>; // 2 x f64 vector value 11 12class Intrinsic<string name> { 13 string Name = name; 14} 15 16class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 17 list<dag> pattern> { 18 bits<8> Opcode = opcode; 19 dag OutOperands = oopnds; 20 dag InOperands = iopnds; 21 string AssemblyString = asmstr; 22 list<dag> Pattern = pattern; 23} 24 25def ops; 26def outs; 27def ins; 28 29def set; 30 31// Define registers 32class Register<string n> { 33 string Name = n; 34} 35 36class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 37 list<ValueType> RegTypes = regTypes; 38 list<Register> MemberList = regList; 39} 40 41def XMM0: Register<"xmm0">; 42def XMM1: Register<"xmm1">; 43def XMM2: Register<"xmm2">; 44def XMM3: Register<"xmm3">; 45def XMM4: Register<"xmm4">; 46def XMM5: Register<"xmm5">; 47def XMM6: Register<"xmm6">; 48def XMM7: Register<"xmm7">; 49def XMM8: Register<"xmm8">; 50def XMM9: Register<"xmm9">; 51def XMM10: Register<"xmm10">; 52def XMM11: Register<"xmm11">; 53def XMM12: Register<"xmm12">; 54def XMM13: Register<"xmm13">; 55def XMM14: Register<"xmm14">; 56def XMM15: Register<"xmm15">; 57 58def VR128 : RegisterClass<[v2i64, v2f64], 59 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 60 XMM8, XMM9, XMM10, XMM11, 61 XMM12, XMM13, XMM14, XMM15]>; 62 63// Dummy for subst 64def REGCLASS : RegisterClass<[], []>; 65 66class decls { 67 // Dummy for foreach 68 dag pattern; 69 int operand; 70} 71 72def Decls : decls; 73 74// Define intrinsics 75def int_x86_sse2_add_ps : Intrinsic<"addps">; 76def int_x86_sse2_add_pd : Intrinsic<"addpd">; 77def INTRINSIC : Intrinsic<"Dummy">; 78 79multiclass arith<bits<8> opcode, string asmstr, string intr, list<dag> patterns> { 80 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), 81 !strconcat(asmstr, "\t$dst, $src1, $src2"), 82 !foreach(Decls.pattern, patterns, 83 !foreach(Decls.operand, Decls.pattern, 84 !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), 85 !subst(REGCLASS, VR128, Decls.operand))))>; 86 87 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), 88 !strconcat(asmstr, "\t$dst, $src1, $src2"), 89 !foreach(Decls.pattern, patterns, 90 !foreach(Decls.operand, Decls.pattern, 91 !subst(INTRINSIC, !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), 92 !subst(REGCLASS, VR128, Decls.operand))))>; 93} 94 95defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX", 96 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>; 97 98