38   : SparcGenRegisterInfo(SP::I7), Subtarget(st) {  in SparcRegisterInfo()
50   Reserved.set(SP::G1);  in getReservedRegs()
54     Reserved.set(SP::G2);  in getReservedRegs()
55     Reserved.set(SP::G3);  in getReservedRegs()
56     Reserved.set(SP::G4);  in getReservedRegs()
60     Reserved.set(SP::G5);  in getReservedRegs()
62   Reserved.set(SP::O6);  in getReservedRegs()
63   Reserved.set(SP::I6);  in getReservedRegs()
64   Reserved.set(SP::I7);  in getReservedRegs()
65   Reserved.set(SP::G0);  in getReservedRegs()
66   Reserved.set(SP::G6);  in getReservedRegs()
67   Reserved.set(SP::G7);  in getReservedRegs()
74   return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;  in getPointerRegClass()
93   unsigned FramePtr = SP::I6;  in eliminateFrameIndex()
96     FramePtr = SP::O6;  in eliminateFrameIndex()
112     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);  in eliminateFrameIndex()
114     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)  in eliminateFrameIndex()
117     MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);  in eliminateFrameIndex()
123   return SP::I6;  in getFrameRegister()