1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcRegisterInfo.h"
15 #include "Sparc.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27
28 #define GET_REGINFO_TARGET_DESC
29 #include "SparcGenRegisterInfo.inc"
30
31 using namespace llvm;
32
33 static cl::opt<bool>
34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35 cl::desc("Reserve application registers (%g2-%g4)"));
36
SparcRegisterInfo(SparcSubtarget & st)37 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
38 : SparcGenRegisterInfo(SP::I7), Subtarget(st) {
39 }
40
getCalleeSavedRegs(const MachineFunction * MF) const41 const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
42 const {
43 static const uint16_t CalleeSavedRegs[] = { 0 };
44 return CalleeSavedRegs;
45 }
46
getReservedRegs(const MachineFunction & MF) const47 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
48 BitVector Reserved(getNumRegs());
49 // FIXME: G1 reserved for now for large imm generation by frame code.
50 Reserved.set(SP::G1);
51
52 // G1-G4 can be used in applications.
53 if (ReserveAppRegisters) {
54 Reserved.set(SP::G2);
55 Reserved.set(SP::G3);
56 Reserved.set(SP::G4);
57 }
58 // G5 is not reserved in 64 bit mode.
59 if (!Subtarget.is64Bit())
60 Reserved.set(SP::G5);
61
62 Reserved.set(SP::O6);
63 Reserved.set(SP::I6);
64 Reserved.set(SP::I7);
65 Reserved.set(SP::G0);
66 Reserved.set(SP::G6);
67 Reserved.set(SP::G7);
68 return Reserved;
69 }
70
71 const TargetRegisterClass*
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const72 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
73 unsigned Kind) const {
74 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
75 }
76
77 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const78 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
79 int SPAdj, unsigned FIOperandNum,
80 RegScavenger *RS) const {
81 assert(SPAdj == 0 && "Unexpected");
82
83 MachineInstr &MI = *II;
84 DebugLoc dl = MI.getDebugLoc();
85 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
86
87 // Addressable stack objects are accessed using neg. offsets from %fp
88 MachineFunction &MF = *MI.getParent()->getParent();
89 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
90 MI.getOperand(FIOperandNum + 1).getImm() +
91 Subtarget.getStackPointerBias();
92 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
93 unsigned FramePtr = SP::I6;
94 if (FuncInfo->isLeafProc()) {
95 // Use %sp and adjust offset if needed.
96 FramePtr = SP::O6;
97 int stackSize = MF.getFrameInfo()->getStackSize();
98 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
99 }
100
101 // Replace frame index with a frame pointer reference.
102 if (Offset >= -4096 && Offset <= 4095) {
103 // If the offset is small enough to fit in the immediate field, directly
104 // encode it.
105 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
106 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
107 } else {
108 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
109 // scavenge a register here instead of reserving G1 all of the time.
110 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
111 unsigned OffHi = (unsigned)Offset >> 10U;
112 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
113 // Emit G1 = G1 + I6
114 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
115 .addReg(FramePtr);
116 // Insert: G1+%lo(offset) into the user.
117 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
118 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
119 }
120 }
121
getFrameRegister(const MachineFunction & MF) const122 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
123 return SP::I6;
124 }
125
getEHExceptionRegister() const126 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
127 llvm_unreachable("What is the exception register");
128 }
129
getEHHandlerRegister() const130 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
131 llvm_unreachable("What is the exception handler register");
132 }
133