| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 225 const MCInstrDesc &MCID) { in BuildMI()
234 const MCInstrDesc &MCID, in BuildMI()
247 const MCInstrDesc &MCID, in BuildMI()
258 const MCInstrDesc &MCID, in BuildMI()
269 const MCInstrDesc &MCID, in BuildMI()
287 const MCInstrDesc &MCID) { in BuildMI()
297 const MCInstrDesc &MCID) { in BuildMI()
307 const MCInstrDesc &MCID) { in BuildMI()
323 const MCInstrDesc &MCID) { in BuildMI()
333 const MCInstrDesc &MCID, in BuildMI()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
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| D | ARMCodeEmitter.cpp | 281 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue() local
487 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
823 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction() local
850 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
1017 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
1099 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction() local
1202 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction() local
1286 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscLoadStoreInstruction() local
1371 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreMultipleInstruction() local
1416 const MCInstrDesc &MCID = MI.getDesc(); in emitMulFrmInstruction() local
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| D | Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
551 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
700 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
764 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow() local
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| D | MLxExpansionPass.cpp | 186 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
343 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
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| D | Thumb1RegisterInfo.cpp | 241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate() local
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate() local
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant() local
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| D | Thumb2ITBlockPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
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| D | ARMBaseRegisterInfo.cpp | 577 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister() local
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| /external/llvm/lib/CodeGen/ |
| D | ScoreboardHazardRecognizer.cpp | 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
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| D | TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
120 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
185 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
220 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
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| D | PeepholeOptimizer.cpp | 421 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
441 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
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| D | MachineVerifier.cpp | 767 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
811 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
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| D | ExecutionDepsFix.cpp | 455 const MCInstrDesc &MCID = MI->getDesc(); in processDefs() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
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| D | SystemZInstrInfo.cpp | 92 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleMove() local
421 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleBD12Move() local
739 const MCInstrDesc &MCID = get(Opcode); in getOpcodeForOffset() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
94 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode); in GetInstrType() local
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| D | PPCRegisterInfo.cpp | 813 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInst.h | 27 const MCInstrDesc *MCID; variable
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
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| D | ScheduleDAGSDNodes.cpp | 299 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
434 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
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| D | InstrEmitter.cpp | 308 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
808 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
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| D | ScheduleDAGRRList.cpp | 1002 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1192 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1318 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
2691 const MCInstrDesc &MCID = TII->get(Opc); in canClobber() local
2918 const MCInstrDesc &MCID = TII->get(Opc); in AddPseudoTwoAddrDeps() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 152 const MCInstrDesc &MCID = MI->getDesc(); variable
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 99 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 551 const MCInstrDesc &MCID = MI.getDesc(); in getInstSizeInBytes() local
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