Searched defs:RegClass (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.h | 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass member
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| D | AArch64AsmPrinter.cpp | 35 const TargetRegisterClass &RegClass, in printModifiedFPRAsmOperand()
53 const TargetRegisterClass &RegClass, in printModifiedGPRAsmOperand()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 596 static bool isVSrc(unsigned RegClass) { in isVSrc()
602 static bool isSSrc(unsigned RegClass) { in isSSrc()
741 unsigned RegClass, in ensureSRegLimit()
815 unsigned RegClass = Desc->OpInfo[Op].RegClass; in foldOperands() local
852 unsigned RegClass = Desc->OpInfo[Op].RegClass; in foldOperands() local
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 46 OwningArrayPtr<RCInfo> RegClass; variable
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| D | RegisterScavenging.h | 156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass; in isSrcOperand() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 432 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32); in selectNode() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| D | TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1580 SDValue RegClass = in createGPRPairNode() local
1591 SDValue RegClass = in createSRegPairNode() local
1602 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in createDRegPairNode() local
1612 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in createQRegPairNode() local
1623 SDValue RegClass = in createQuadSRegsNode() local
1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in createQuadDRegsNode() local
1652 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); in createQuadQRegsNode() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 900 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1261 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; in computeUberSets() local
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| D | CodeGenDAGPatterns.cpp | 1341 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 278 unsigned &RegClass, unsigned &Cost, in GetCostForDef()
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