D | assembler_arm.cc | 143 ShifterOperand so) { in EmitType01() argument 152 so.encoding(); in EmitType01() 219 ShifterOperand so) { in EmitShiftImmediate() argument 221 CHECK_EQ(so.type(), 1U); in EmitShiftImmediate() 225 so.encoding() << kShiftImmShift | in EmitShiftImmediate() 236 ShifterOperand so) { in EmitShiftRegister() argument 238 CHECK_EQ(so.type(), 0U); in EmitShiftRegister() 242 so.encoding() << kShiftRegisterShift | in EmitShiftRegister() 261 void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so, in and_() argument 263 EmitType01(cond, so.type(), AND, 0, rn, rd, so); in and_() [all …]
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