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Searched refs:lowReg (Results 1 – 22 of 22) sorted by relevance

/dalvik/vm/compiler/codegen/
DCodegenFactory.cpp58 genRegCopy(cUnit, reg1, rlSrc.lowReg); in loadValueDirect()
91 genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg); in loadValueDirectWide()
124 loadValueDirect(cUnit, rlSrc, rlSrc.lowReg); in loadValue()
126 dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow); in loadValue()
129 rlSrc.lowReg); in loadValue()
131 dvmCompilerClobber(cUnit, rlSrc.lowReg); in loadValue()
147 if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) || in storeValue()
151 genRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg); in storeValue()
154 rlDest.lowReg = rlSrc.lowReg; in storeValue()
155 dvmCompilerClobber(cUnit, rlSrc.lowReg); in storeValue()
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DRallocUtil.cpp469 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerMarkDef()
485 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerMarkDefWide()
496 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg); in dvmCompilerWideToNarrow()
527 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerResetDefLoc()
532 dvmCompilerResetDef(cUnit, rl.lowReg); in dvmCompilerResetDefLoc()
539 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerResetDefLocWide()
544 dvmCompilerResetDef(cUnit, rl.lowReg); in dvmCompilerResetDefLocWide()
632 extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg, int highReg) in dvmCompilerMarkPair() argument
634 RegisterInfo *infoLo = getRegInfo(cUnit, lowReg); in dvmCompilerMarkPair()
638 infoHi->partner = lowReg; in dvmCompilerMarkPair()
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DRalloc.h98 extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg,
/dalvik/vm/compiler/codegen/mips/Mips32/
DRalloc.cpp33 int lowReg; in dvmCompilerAllocTypedTempPair() local
38 lowReg = dvmCompilerAllocTempDouble(cUnit); in dvmCompilerAllocTypedTempPair()
39 highReg = lowReg + 1; in dvmCompilerAllocTypedTempPair()
40 res = (lowReg & 0xff) | ((highReg & 0xff) << 8); in dvmCompilerAllocTypedTempPair()
45 lowReg = dvmCompilerAllocTemp(cUnit); in dvmCompilerAllocTypedTempPair()
47 res = (lowReg & 0xff) | ((highReg & 0xff) << 8); in dvmCompilerAllocTypedTempPair()
DGen.cpp87 opRegRegImm(cUnit, kOpAdd, rlResult.lowReg, in genNegFloat()
88 rlSrc.lowReg, 0x80000000); in genNegFloat()
100 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg); in genNegDouble()
125 newLIR3(cUnit, opc, rlDest.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); in withCarryHelper()
148 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
152 rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
155 newLIR2(cUnit, kMipsMove, tReg, rlResult.lowReg); in genLong3Addr()
157 tReg, rlResult.lowReg); in genLong3Addr()
165 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlResult.lowReg); in genLong3Addr()
169 rlResult.lowReg, rlSrc1.lowReg); in genLong3Addr()
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DFactory.cpp32 static void storePair(CompilationUnit *cUnit, int base, int lowReg,
34 static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
823 static void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in storePair() argument
825 storeWordDisp(cUnit, base, LOWORD_OFFSET, lowReg); in storePair()
829 static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in loadPair() argument
831 loadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg); in loadPair()
/dalvik/vm/compiler/codegen/mips/
DCodegenFactory.cpp52 genRegCopy(cUnit, reg1, rlSrc.lowReg); in loadValueDirect()
85 genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg); in loadValueDirectWide()
117 loadValueDirect(cUnit, rlSrc, rlSrc.lowReg); in loadValue()
119 dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow); in loadValue()
121 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), rlSrc.lowReg); in loadValue()
123 dvmCompilerClobber(cUnit, rlSrc.lowReg); in loadValue()
139 if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) || in storeValue()
143 genRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg); in storeValue()
146 rlDest.lowReg = rlSrc.lowReg; in storeValue()
147 dvmCompilerClobber(cUnit, rlSrc.lowReg); in storeValue()
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DRallocUtil.cpp535 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerMarkDef()
551 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerMarkDefWide()
562 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg); in dvmCompilerWideToNarrow()
599 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerResetDefLoc()
604 dvmCompilerResetDef(cUnit, rl.lowReg); in dvmCompilerResetDefLoc()
611 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg); in dvmCompilerResetDefLocWide()
616 dvmCompilerResetDef(cUnit, rl.lowReg); in dvmCompilerResetDefLocWide()
704 extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg, int highReg) in dvmCompilerMarkPair() argument
706 RegisterInfo *infoLo = getRegInfo(cUnit, lowReg); in dvmCompilerMarkPair()
710 infoHi->partner = lowReg; in dvmCompilerMarkPair()
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DCodegenDriver.cpp377 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIGetWide()
379 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset); in genIGetWide()
383 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg); in genIGetWide()
398 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIPutWide()
401 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset); in genIPutWide()
404 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg); in genIPutWide()
423 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIGet()
427 loadBaseDisp(cUnit, mir, rlObj.lowReg, fieldOffset, rlResult.lowReg, in genIGet()
449 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIPut()
456 storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size); in genIPut()
[all …]
DRalloc.h102 extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg,
/dalvik/vm/compiler/codegen/arm/FP/
DThumb2VFP.cpp57 newLIR3(cUnit, (ArmOpcode)op, rlResult.lowReg, rlSrc1.lowReg, in genArithOpFloat()
58 rlSrc2.lowReg); in genArithOpFloat()
104 newLIR3(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg), in genArithOpDouble()
105 S2D(rlSrc1.lowReg, rlSrc1.highReg), in genArithOpDouble()
106 S2D(rlSrc2.lowReg, rlSrc2.highReg)); in genArithOpDouble()
164 srcReg = S2D(rlSrc.lowReg, rlSrc.highReg); in genConversion()
168 srcReg = rlSrc.lowReg; in genConversion()
173 newLIR2(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg), in genConversion()
179 newLIR2(cUnit, (ArmOpcode)op, rlResult.lowReg, srcReg); in genConversion()
192 newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg), in genInlineSqrt()
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DThumbVFP.cpp34 dvmCompilerFlushRegWide(cUnit, rlSrc.lowReg, rlSrc.highReg); in loadValueAddressDirect()
36 dvmCompilerFlushReg(cUnit, rlSrc.lowReg); in loadValueAddressDirect()
105 dvmCompilerClobber(cUnit, rlDest.lowReg); in genArithOpFloat()
148 dvmCompilerClobber(cUnit, rlDest.lowReg); in genArithOpDouble()
222 dvmCompilerClobber(cUnit, rlDest.lowReg); in genConversion()
/dalvik/vm/compiler/codegen/arm/Thumb2/
DRalloc.cpp36 int lowReg; in dvmCompilerAllocTypedTempPair() local
44 lowReg = dvmCompilerAllocTempDouble(cUnit); in dvmCompilerAllocTypedTempPair()
45 highReg = lowReg + 1; in dvmCompilerAllocTypedTempPair()
47 lowReg = dvmCompilerAllocTemp(cUnit); in dvmCompilerAllocTypedTempPair()
50 res = (lowReg & 0xff) | ((highReg & 0xff) << 8); in dvmCompilerAllocTypedTempPair()
DGen.cpp82 newLIR2(cUnit, kThumb2Vnegs, rlResult.lowReg, rlSrc.lowReg); in genNegFloat()
92 newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg), in genNegDouble()
93 S2D(rlSrc.lowReg, rlSrc.highReg)); in genNegDouble()
113 newLIR3(cUnit, kThumb2MulRRR, tmp1, rlSrc2.lowReg, rlSrc1.highReg); in genMulLong()
114 newLIR4(cUnit, kThumb2Umull, resLo, resHi, rlSrc2.lowReg, rlSrc1.lowReg); in genMulLong()
115 newLIR4(cUnit, kThumb2Mla, tmp1, rlSrc1.lowReg, rlSrc2.highReg, tmp1); in genMulLong()
120 rlResult.lowReg = resLo; in genMulLong()
133 opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); in genLong3Addr()
379 rlTemp.lowReg = dvmCompilerAllocTemp(cUnit); in genCmpLong()
380 loadConstant(cUnit, rlTemp.lowReg, -1); in genCmpLong()
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DFactory.cpp1151 static void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in storePair() argument
1153 storeBaseDispWide(cUnit, base, 0, lowReg, highReg); in storePair()
1156 static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in loadPair() argument
1158 loadBaseDispWide(cUnit, NULL, base, 0, lowReg, highReg, INVALID_SREG); in loadPair()
/dalvik/vm/compiler/codegen/arm/Thumb/
DGen.cpp91 opRegRegImm(cUnit, kOpAdd, rlResult.lowReg, in genNegFloat()
92 rlSrc.lowReg, 0x80000000); in genNegFloat()
104 genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg); in genNegDouble()
138 opRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
145 opRegReg(cUnit, firstOp, rlSrc1.lowReg, rlResult.lowReg); in genLong3Addr()
148 dvmCompilerClobber(cUnit, rlResult.lowReg); in genLong3Addr()
150 dvmCompilerClobber(cUnit, rlSrc1.lowReg); in genLong3Addr()
160 loadValueDirectWide(cUnit, rlSrc1, rlResult.lowReg, in genLong3Addr()
163 opRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc2.lowReg); in genLong3Addr()
219 int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg; in genInlinedAbsFloat()
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DRalloc.cpp33 int lowReg; in dvmCompilerAllocTypedTempPair() local
35 lowReg = dvmCompilerAllocTemp(cUnit); in dvmCompilerAllocTypedTempPair()
37 res = (lowReg & 0xff) | ((highReg & 0xff) << 8); in dvmCompilerAllocTypedTempPair()
DFactory.cpp27 static void storePair(CompilationUnit *cUnit, int base, int lowReg,
29 static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
819 static void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in storePair() argument
821 if (lowReg < highReg) { in storePair()
822 storeMultiple(cUnit, base, (1 << lowReg) | (1 << highReg)); in storePair()
824 storeWordDisp(cUnit, base, 0, lowReg); in storePair()
829 static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg) in loadPair() argument
831 if (lowReg < highReg) { in loadPair()
832 loadMultiple(cUnit, base, (1 << lowReg) | (1 << highReg)); in loadPair()
834 loadWordDisp(cUnit, base, 0 , lowReg); in loadPair()
/dalvik/vm/compiler/codegen/mips/FP/
DMipsFP.cpp34 dvmCompilerFlushRegWideForV5TEVFP(cUnit, rlSrc.lowReg, in loadValueAddress()
37 dvmCompilerFlushRegForV5TEVFP(cUnit, rlSrc.lowReg); in loadValueAddress()
107 newLIR3(cUnit, (MipsOpCode)op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg); in genArithOpFloat()
151 dvmCompilerClobber(cUnit, rlDest.lowReg); in genArithOpFloat()
197 newLIR3(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg), in genArithOpDouble()
198 S2D(rlSrc1.lowReg, rlSrc1.highReg), in genArithOpDouble()
199 S2D(rlSrc2.lowReg, rlSrc2.highReg)); in genArithOpDouble()
239 dvmCompilerClobber(cUnit, rlDest.lowReg); in genArithOpDouble()
292 srcReg = S2D(rlSrc.lowReg, rlSrc.highReg); in genConversion()
296 srcReg = rlSrc.lowReg; in genConversion()
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/dalvik/vm/compiler/codegen/arm/
DArmRallocUtil.cpp83 dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg); in dvmCompilerGetReturnWide()
90 res.lowReg = r2; in dvmCompilerGetReturnWideAlt()
96 dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg); in dvmCompilerGetReturnWideAlt()
111 res.lowReg = r1; in dvmCompilerGetReturnAlt()
DCodegenDriver.cpp311 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIGetWide()
313 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset); in genIGetWide()
317 loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg); in genIGetWide()
332 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIPutWide()
335 opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset); in genIPutWide()
338 storePair(cUnit, regPtr, rlSrc.lowReg, rlSrc.highReg); in genIPutWide()
357 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIGet()
361 loadBaseDisp(cUnit, mir, rlObj.lowReg, fieldOffset, rlResult.lowReg, in genIGet()
383 genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, in genIPut()
390 storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, size); in genIPut()
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/dalvik/vm/compiler/
DCompilerIR.h42 u1 lowReg:6; // First physical register member