| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList, 4)) in f64AssignAPCS()
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); in f64AssignAAPCS()
83 Reg = State.AllocateReg(GPRArgRegs, 4); in f64AssignAAPCS()
102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); in f64RetAssign()
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| D | ARMISelLowering.cpp | 1797 unsigned reg = State->AllocateReg(GPRArgRegs, 4); in HandleByVal()
1823 reg = State->AllocateReg(GPRArgRegs, 4); in HandleByVal()
1833 while (State->AllocateReg(GPRArgRegs, 4)) in HandleByVal()
1850 State->AllocateReg(GPRArgRegs, 4); in HandleByVal()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConvLower.h | 120 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
127 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
137 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() function
149 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() function
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| D | HexagonVarargsCallingConvention.h | 56 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { in CC_Hexagon32_VarArgs()
68 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { in CC_Hexagon32_VarArgs()
112 if (unsigned Reg = State.AllocateReg(RegList1, 6)) { in RetCC_Hexagon32_VarArgs()
124 if (unsigned Reg = State.AllocateReg(RegList2, 3)) { in RetCC_Hexagon32_VarArgs()
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| D | HexagonISelLowering.cpp | 177 if (unsigned Reg = State.AllocateReg(RegList, 6)) { in CC_Hexagon32()
191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in CC_Hexagon64()
202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { in CC_Hexagon64()
248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { in RetCC_Hexagon32()
263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in RetCC_Hexagon64()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 291 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function
298 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { in AllocateReg() function
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, in AllocateReg() function
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 192 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
193 CCInfo.AllocateReg(AMDGPU::VGPR1); in LowerFormalArguments()
198 CCInfo.AllocateReg(AMDGPU::SGPR0); in LowerFormalArguments()
199 CCInfo.AllocateReg(AMDGPU::SGPR1); in LowerFormalArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2197 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2201 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2206 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2208 Reg = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2209 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2214 Reg = State.AllocateReg(F32Regs, FloatRegsSize); in CC_MipsO32()
2216 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2218 Reg = State.AllocateReg(F64Regs, FloatRegsSize); in CC_MipsO32()
2220 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
2222 State.AllocateReg(IntRegs, IntRegsSize); in CC_MipsO32()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 58 if (unsigned Reg = State.AllocateReg(RegList, 6)) { in CC_Sparc_Assign_f64()
69 if (unsigned Reg = State.AllocateReg(RegList, 6)) in CC_Sparc_Assign_f64()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 860 State.AllocateReg(AArch64ArgRegs[i]); in CC_AArch64NoMoreRegs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1842 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1868 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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