| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 197 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
201 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
203 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
211 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
218 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
223 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 103 unsigned DefIdx) const { in getWriteLatencyEntry() argument
104 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
107 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 129 unsigned DefIdx = 0; in findDefIdx() local
133 ++DefIdx; in findDefIdx()
135 return DefIdx; in findDefIdx()
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
190 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
193 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
216 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
237 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in computeInstrLatency() local
238 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
241 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeInstrLatency()
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| D | TargetInstrInfo.cpp | 575 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
585 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
647 unsigned DefIdx) const { in hasLowDefLatency()
652 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
660 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
664 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
697 const MachineInstr *DefMI, unsigned DefIdx, in computeOperandLatency() argument
708 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
711 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
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| D | LiveRangeEdit.cpp | 121 SlotIndex DefIdx; in canRematerializeAt() local
123 DefIdx = LIS.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
125 DefIdx = RM.ParentVNI->def; in canRematerializeAt()
126 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); in canRematerializeAt()
135 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| D | LiveRangeCalc.cpp | 91 unsigned DefIdx; in extendToUses() local
95 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) { in extendToUses()
98 if (MI->getOperand(DefIdx).isEarlyClobber()) in extendToUses()
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| D | MachineInstr.cpp | 700 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
701 if (DefIdx != -1) in addOperand()
702 tieOperands(DefIdx, OpNo); in addOperand()
963 unsigned DefIdx; in getRegClassConstraint() local
964 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
965 OpIdx = DefIdx; in getRegClassConstraint()
1109 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1110 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1117 if (DefIdx < TiedMax) in tieOperands()
1118 UseMO.TiedTo = DefIdx + 1; in tieOperands()
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| D | MachineVerifier.cpp | 881 unsigned DefIdx; in visitMachineOperand() local
883 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
884 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1077 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
1078 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
1081 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { in checkLiveness()
1083 if (VNI->def != DefIdx) { in checkLiveness()
1086 << DefIdx << " in " << LI << '\n'; in checkLiveness()
1090 *OS << DefIdx << " is not live in " << LI << '\n'; in checkLiveness()
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| D | InlineSpiller.cpp | 892 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM, in reMaterializeFor() local
894 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' in reMaterializeFor()
895 << *LIS.getInstructionFromIndex(DefIdx)); in reMaterializeFor()
907 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, LIS.getVNInfoAllocator()); in reMaterializeFor()
908 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI)); in reMaterializeFor()
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| D | RegisterCoalescer.cpp | 600 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef() local
601 assert(DefIdx != -1); in removeCopyByCommutingDef()
603 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
703 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef() local
704 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); in removeCopyByCommutingDef()
707 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); in removeCopyByCommutingDef()
708 assert(DVNI->def == DefIdx); in removeCopyByCommutingDef()
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| D | RegAllocFast.cpp | 732 unsigned DefIdx = 0; in handleThroughOperands() local
733 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; in handleThroughOperands()
735 << DefIdx << ".\n"); in handleThroughOperands()
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| D | MachineLICM.cpp | 200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
1010 unsigned DefIdx, unsigned Reg) const { in HasHighOperandLatency() argument
1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) in HasHighOperandLatency()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 223 const MachineInstr *DefMI, unsigned DefIdx,
227 SDNode *DefNode, unsigned DefIdx,
248 unsigned DefIdx, unsigned DefAlign) const;
252 unsigned DefIdx, unsigned DefAlign) const;
263 unsigned DefIdx, unsigned DefAlign,
276 const MachineInstr *DefMI, unsigned DefIdx,
279 const MachineInstr *DefMI, unsigned DefIdx) const;
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| D | ARMBaseInstrInfo.cpp | 2791 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
2792 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
2795 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
2832 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
2833 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
2836 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
2935 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
2941 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
2942 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
2951 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
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| D | ARMISelDAGToDAG.cpp | 3537 unsigned DefIdx = 0; in SelectInlineAsm() local
3541 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in SelectInlineAsm()
3542 IsTiedToChangedOp = OpChanged[DefIdx]; in SelectInlineAsm()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 794 SDNode *DefNode, unsigned DefIdx,
806 const MachineInstr *DefMI, unsigned DefIdx,
813 const MachineInstr *DefMI, unsigned DefIdx,
846 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
855 const MachineInstr *DefMI, unsigned DefIdx) const;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 136 unsigned DefIdx; variable
154 return DefIdx-1; in GetIdx()
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| D | ScheduleDAGSDNodes.cpp | 548 DefIdx = 0; in InitNodeNumDefs()
554 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
562 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
563 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
565 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
566 ++DefIdx; in Advance()
628 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
632 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
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| D | InstrEmitter.cpp | 955 unsigned DefIdx = GroupIdx[DefGroup] + 1; in EmitSpecialNode() local
958 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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| /external/llvm/include/llvm/CodeGen/ |
| D | TargetSchedule.h | 160 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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| D | MachineInstr.h | 832 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 385 const MachineInstr *DefMI, unsigned DefIdx,
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| D | X86InstrInfo.cpp | 5011 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
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