1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
16
17 #include "ARM.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
25
26 namespace llvm {
27 class ARMSubtarget;
28 class ARMBaseRegisterInfo;
29
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
32
33 protected:
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37 public:
38 // Return whether the target has an explicit NOP encoding.
39 bool hasNOP() const;
40
41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
42 // if there is not such an opcode.
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
44
45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46 MachineBasicBlock::iterator &MBBI,
47 LiveVariables *LV) const;
48
49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()50 const ARMSubtarget &getSubtarget() const { return Subtarget; }
51
52 ScheduleHazardRecognizer *
53 CreateTargetHazardRecognizer(const TargetMachine *TM,
54 const ScheduleDAG *DAG) const;
55
56 ScheduleHazardRecognizer *
57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58 const ScheduleDAG *DAG) const;
59
60 // Branch analysis.
61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify = false) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
69 DebugLoc DL) const;
70
71 virtual
72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
73
74 // Predication support.
75 bool isPredicated(const MachineInstr *MI) const;
76
getPredicate(const MachineInstr * MI)77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80 : ARMCC::AL;
81 }
82
83 virtual
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
86
87 virtual
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
90
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
93
94 virtual bool isPredicable(MachineInstr *MI) const;
95
96 /// GetInstSize - Returns the size of the specified MachineInstr.
97 ///
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
99
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
108
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
112 bool KillSrc) const;
113
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
119
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
125
126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
127
128 virtual void reMaterialize(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MI,
130 unsigned DestReg, unsigned SubIdx,
131 const MachineInstr *Orig,
132 const TargetRegisterInfo &TRI) const;
133
134 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
135
136 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
137
138 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
139 unsigned SubIdx, unsigned State,
140 const TargetRegisterInfo *TRI) const;
141
142 virtual bool produceSameValue(const MachineInstr *MI0,
143 const MachineInstr *MI1,
144 const MachineRegisterInfo *MRI) const;
145
146 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
147 /// determine if two loads are loading from the same base address. It should
148 /// only return true if the base pointers are the same and the only
149 /// differences between the two addresses is the offset. It also returns the
150 /// offsets by reference.
151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
152 int64_t &Offset1, int64_t &Offset2)const;
153
154 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
155 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
156 /// should be scheduled togther. On some targets if two loads are loading from
157 /// addresses in the same cache line, it's better if they are scheduled
158 /// together. This function takes two integers that represent the load offsets
159 /// from the common base address. It returns true if it decides it's desirable
160 /// to schedule the two loads together. "NumLoads" is the number of loads that
161 /// have already been scheduled after Load1.
162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
163 int64_t Offset1, int64_t Offset2,
164 unsigned NumLoads) const;
165
166 virtual bool isSchedulingBoundary(const MachineInstr *MI,
167 const MachineBasicBlock *MBB,
168 const MachineFunction &MF) const;
169
170 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
171 unsigned NumCycles, unsigned ExtraPredCycles,
172 const BranchProbability &Probability) const;
173
174 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
175 unsigned NumT, unsigned ExtraT,
176 MachineBasicBlock &FMBB,
177 unsigned NumF, unsigned ExtraF,
178 const BranchProbability &Probability) const;
179
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,const BranchProbability & Probability)180 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
181 unsigned NumCycles,
182 const BranchProbability
183 &Probability) const {
184 return NumCycles == 1;
185 }
186
187 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
188 MachineBasicBlock &FMBB) const;
189
190 /// analyzeCompare - For a comparison instruction, return the source registers
191 /// in SrcReg and SrcReg2 if having two register operands, and the value it
192 /// compares against in CmpValue. Return true if the comparison instruction
193 /// can be analyzed.
194 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
195 unsigned &SrcReg2, int &CmpMask,
196 int &CmpValue) const;
197
198 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
199 /// that we can remove a "comparison with zero"; Remove a redundant CMP
200 /// instruction if the flags can be updated in the same way by an earlier
201 /// instruction such as SUB.
202 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
203 unsigned SrcReg2, int CmpMask, int CmpValue,
204 const MachineRegisterInfo *MRI) const;
205
206 virtual bool analyzeSelect(const MachineInstr *MI,
207 SmallVectorImpl<MachineOperand> &Cond,
208 unsigned &TrueOp, unsigned &FalseOp,
209 bool &Optimizable) const;
210
211 virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
212
213 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
214 /// instruction, try to fold the immediate into the use instruction.
215 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
216 unsigned Reg, MachineRegisterInfo *MRI) const;
217
218 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
219 const MachineInstr *MI) const;
220
221 virtual
222 int getOperandLatency(const InstrItineraryData *ItinData,
223 const MachineInstr *DefMI, unsigned DefIdx,
224 const MachineInstr *UseMI, unsigned UseIdx) const;
225 virtual
226 int getOperandLatency(const InstrItineraryData *ItinData,
227 SDNode *DefNode, unsigned DefIdx,
228 SDNode *UseNode, unsigned UseIdx) const;
229
230 /// VFP/NEON execution domains.
231 std::pair<uint16_t, uint16_t>
232 getExecutionDomain(const MachineInstr *MI) const;
233 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
234
235 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
236 const TargetRegisterInfo*) const;
237 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
238 const TargetRegisterInfo *TRI) const;
239 /// Get the number of addresses by LDM or VLDM or zero for unknown.
240 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
241
242 private:
243 unsigned getInstBundleLength(const MachineInstr *MI) const;
244
245 int getVLDMDefCycle(const InstrItineraryData *ItinData,
246 const MCInstrDesc &DefMCID,
247 unsigned DefClass,
248 unsigned DefIdx, unsigned DefAlign) const;
249 int getLDMDefCycle(const InstrItineraryData *ItinData,
250 const MCInstrDesc &DefMCID,
251 unsigned DefClass,
252 unsigned DefIdx, unsigned DefAlign) const;
253 int getVSTMUseCycle(const InstrItineraryData *ItinData,
254 const MCInstrDesc &UseMCID,
255 unsigned UseClass,
256 unsigned UseIdx, unsigned UseAlign) const;
257 int getSTMUseCycle(const InstrItineraryData *ItinData,
258 const MCInstrDesc &UseMCID,
259 unsigned UseClass,
260 unsigned UseIdx, unsigned UseAlign) const;
261 int getOperandLatency(const InstrItineraryData *ItinData,
262 const MCInstrDesc &DefMCID,
263 unsigned DefIdx, unsigned DefAlign,
264 const MCInstrDesc &UseMCID,
265 unsigned UseIdx, unsigned UseAlign) const;
266
267 unsigned getInstrLatency(const InstrItineraryData *ItinData,
268 const MachineInstr *MI,
269 unsigned *PredCost = 0) const;
270
271 int getInstrLatency(const InstrItineraryData *ItinData,
272 SDNode *Node) const;
273
274 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
275 const MachineRegisterInfo *MRI,
276 const MachineInstr *DefMI, unsigned DefIdx,
277 const MachineInstr *UseMI, unsigned UseIdx) const;
278 bool hasLowDefLatency(const InstrItineraryData *ItinData,
279 const MachineInstr *DefMI, unsigned DefIdx) const;
280
281 /// verifyInstruction - Perform target specific instruction verification.
282 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
283
284 private:
285 /// Modeling special VFP / NEON fp MLA / MLS hazards.
286
287 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
288 /// MLx table.
289 DenseMap<unsigned, unsigned> MLxEntryMap;
290
291 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
292 /// stalls when scheduled together with fp MLA / MLS opcodes.
293 SmallSet<unsigned, 16> MLxHazardOpcodes;
294
295 public:
296 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
297 /// instruction.
isFpMLxInstruction(unsigned Opcode)298 bool isFpMLxInstruction(unsigned Opcode) const {
299 return MLxEntryMap.count(Opcode);
300 }
301
302 /// isFpMLxInstruction - This version also returns the multiply opcode and the
303 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
304 /// the MLX instructions with an extra lane operand.
305 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
306 unsigned &AddSubOpc, bool &NegAcc,
307 bool &HasLane) const;
308
309 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
310 /// will cause stalls when scheduled after (within 4-cycle window) a fp
311 /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)312 bool canCauseFpMLxStall(unsigned Opcode) const {
313 return MLxHazardOpcodes.count(Opcode);
314 }
315
316 /// Returns true if the instruction has a shift by immediate that can be
317 /// executed in one cycle less.
318 bool isSwiftFastImmShift(const MachineInstr *MI) const;
319 };
320
321 static inline
AddDefaultPred(const MachineInstrBuilder & MIB)322 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
323 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
324 }
325
326 static inline
AddDefaultCC(const MachineInstrBuilder & MIB)327 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
328 return MIB.addReg(0);
329 }
330
331 static inline
332 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
333 bool isDead = false) {
334 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
335 }
336
337 static inline
AddNoT1CC(const MachineInstrBuilder & MIB)338 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
339 return MIB.addReg(0);
340 }
341
342 static inline
isUncondBranchOpcode(int Opc)343 bool isUncondBranchOpcode(int Opc) {
344 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
345 }
346
347 static inline
isCondBranchOpcode(int Opc)348 bool isCondBranchOpcode(int Opc) {
349 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
350 }
351
352 static inline
isJumpTableBranchOpcode(int Opc)353 bool isJumpTableBranchOpcode(int Opc) {
354 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
355 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
356 }
357
358 static inline
isIndirectBranchOpcode(int Opc)359 bool isIndirectBranchOpcode(int Opc) {
360 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
361 }
362
363 /// getInstrPredicate - If instruction is predicated, returns its predicate
364 /// condition, otherwise returns AL. It also returns the condition code
365 /// register by reference.
366 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
367
368 int getMatchingCondBranchOpcode(int Opc);
369
370 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
371 /// opcode of the SSA instruction representing the conditional MI.
372 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
373 MachineInstr *&MI,
374 const MachineRegisterInfo &MRI);
375
376 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
377 /// the instruction is encoded with an 'S' bit is determined by the optional
378 /// CPSR def operand.
379 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
380
381 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
382 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
383 /// code.
384 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
385 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
386 unsigned DestReg, unsigned BaseReg, int NumBytes,
387 ARMCC::CondCodes Pred, unsigned PredReg,
388 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
389
390 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
392 unsigned DestReg, unsigned BaseReg, int NumBytes,
393 ARMCC::CondCodes Pred, unsigned PredReg,
394 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
395 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
397 unsigned DestReg, unsigned BaseReg,
398 int NumBytes, const TargetInstrInfo &TII,
399 const ARMBaseRegisterInfo& MRI,
400 unsigned MIFlags = 0);
401
402
403 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
404 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
405 /// offset could not be handled directly in MI, and return the left-over
406 /// portion by reference.
407 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
408 unsigned FrameReg, int &Offset,
409 const ARMBaseInstrInfo &TII);
410
411 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
412 unsigned FrameReg, int &Offset,
413 const ARMBaseInstrInfo &TII);
414
415 } // End llvm namespace
416
417 #endif
418