/external/valgrind/main/none/tests/arm/ |
D | vfp.stdout.exp | 726 vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5 727 vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000 728 vcmp.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000 729 vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd 730 vcmp.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666 731 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000 732 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40280bc6 a7ef9db2 Dm 0x40280bc6 a7ef9db2 733 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x00000000 00000000 Dm 0x00000000 00000000 734 vcmp.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000 735 vcmp.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000 [all …]
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/external/valgrind/main/none/tests/ppc32/ |
D | test_dfp1.stdout.exp | 571 Test move to/from FPSCR 572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes 573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes 574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes 575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes 576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes 577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes 578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes 579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes 580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes [all …]
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/external/valgrind/main/none/tests/ppc64/ |
D | test_dfp1.stdout.exp | 571 Test move to/from FPSCR 572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes 573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes 574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes 575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes 576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes 577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes 578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes 579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes 580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 159 // We model fpscr with two registers: FPSCR models the control bits and will be 167 def FPSCR : ARMReg<3, "fpscr">; 169 let Aliases = [FPSCR];
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D | ARMInstrVFP.td | 1015 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1016 let Uses = [FPSCR] in { 1501 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1507 // Application level FPSCR -> GPR 1508 let hasSideEffects = 1, Uses = [FPSCR] in 1514 let Uses = [FPSCR] in { 1550 let Defs = [FPSCR] in { 1551 // Application level GPR -> FPSCR
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D | ARMBaseRegisterInfo.cpp | 109 Reserved.set(ARM::FPSCR); in getReservedRegs()
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D | ARMScheduleSwift.td | 1661 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
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D | ARMISelLowering.cpp | 3801 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in LowerFLT_ROUNDS_() local 3804 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
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/external/valgrind/main/VEX/priv/ |
D | host_arm_defs.c | 1369 i->ARMin.FPSCR.toFPSCR = toFPSCR; in ARMInstr_FPSCR() 1370 i->ARMin.FPSCR.iReg = iReg; in ARMInstr_FPSCR() 1833 if (i->ARMin.FPSCR.toFPSCR) { in ppARMInstr() 1835 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr() 1838 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr() 2206 if (i->ARMin.FPSCR.toFPSCR) in getRegUsage_ARMInstr() 2207 addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr() 2209 addHRegUse(u, HRmWrite, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr() 2416 i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg); in mapRegs_ARMInstr() 3642 Bool toFPSCR = i->ARMin.FPSCR.toFPSCR; in emit_ARMInstr() [all …]
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D | host_arm_defs.h | 849 } FPSCR; member
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.td | 83 // Extract FPSCR (not modeled at the DAG level). 1701 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR! 1946 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
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/external/oprofile/events/ppc64/power6/ |
D | events | 754 … minimum:1000 name:PM_FPU0_FPSCR_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 executed FPSCR instruction 778 … minimum:1000 name:PM_FPU1_FPSCR_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 executed FPSCR instruction 796 …zero minimum:1000 name:PM_FPU_FPSCR_GRP129 : (Group 129 pm_fpu_misc) FPU executed FPSCR instruction
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/external/valgrind/main/memcheck/ |
D | mc_machine.c | 881 if (o == GOF(FPSCR) && sz == 4) return -1; in get_otrack_shadow_offset_wrk()
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/external/oprofile/events/ppc64/970MP/ |
D | events | 160 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
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/external/oprofile/events/ppc64/970/ |
D | events | 155 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
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/external/oprofile/events/ppc64/power5++/ |
D | events | 557 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction 863 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
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/external/oprofile/events/ppc64/power5/ |
D | events | 704 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP86 : (Group 86 pm_fpu8) FPU0 executed FPSCR instruction 1096 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP135 : (Group 135 pm_fpuX1) FPU0 executed FPSCR instruction
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/external/oprofile/events/ppc64/power5+/ |
D | events | 728 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction 1136 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
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/external/oprofile/events/ppc64/power4/ |
D | events | 345 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP33 : (Group 33 pm_fpu7) FPU0 executed FPSCR instruction
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/external/v8/ |
D | ChangeLog | 1556 Avoided trashing the FPSCR when calculating Math.floor on ARM.
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/external/chromium_org/v8/ |
D | ChangeLog | 3988 Avoided trashing the FPSCR when calculating Math.floor on ARM.
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/external/oprofile/events/ppc64/power7/ |
D | events | 1104 …inimum:1000 name:PM_VSU0_FPSCR_GRP136 : (Group 136 pm_vsu15) Move to/from FPSCR type instruction i…
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