1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM VFP instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 15def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 16def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 17def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 18 SDTCisSameAs<1, 2>]>; 19 20def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; 21def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; 22def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; 23def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; 24def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 25def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 26def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 27def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 28 29 30//===----------------------------------------------------------------------===// 31// Operand Definitions. 32// 33 34// 8-bit floating-point immediate encodings. 35def FPImmOperand : AsmOperandClass { 36 let Name = "FPImm"; 37 let ParserMethod = "parseFPImm"; 38} 39 40def vfp_f32imm : Operand<f32>, 41 PatLeaf<(f32 fpimm), [{ 42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 43 }], SDNodeXForm<fpimm, [{ 44 APFloat InVal = N->getValueAPF(); 45 uint32_t enc = ARM_AM::getFP32Imm(InVal); 46 return CurDAG->getTargetConstant(enc, MVT::i32); 47 }]>> { 48 let PrintMethod = "printFPImmOperand"; 49 let ParserMatchClass = FPImmOperand; 50} 51 52def vfp_f64imm : Operand<f64>, 53 PatLeaf<(f64 fpimm), [{ 54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 55 }], SDNodeXForm<fpimm, [{ 56 APFloat InVal = N->getValueAPF(); 57 uint32_t enc = ARM_AM::getFP64Imm(InVal); 58 return CurDAG->getTargetConstant(enc, MVT::i32); 59 }]>> { 60 let PrintMethod = "printFPImmOperand"; 61 let ParserMatchClass = FPImmOperand; 62} 63 64def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 65 return cast<LoadSDNode>(N)->getAlignment() >= 4; 66}]>; 67 68def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 69 (store node:$val, node:$ptr), [{ 70 return cast<StoreSDNode>(N)->getAlignment() >= 4; 71}]>; 72 73// The VCVT to/from fixed-point instructions encode the 'fbits' operand 74// (the number of fixed bits) differently than it appears in the assembly 75// source. It's encoded as "Size - fbits" where Size is the size of the 76// fixed-point representation (32 or 16) and fbits is the value appearing 77// in the assembly source, an integer in [0,16] or (0,32], depending on size. 78def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 79def fbits32 : Operand<i32> { 80 let PrintMethod = "printFBits32"; 81 let ParserMatchClass = fbits32_asm_operand; 82} 83 84def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 85def fbits16 : Operand<i32> { 86 let PrintMethod = "printFBits16"; 87 let ParserMatchClass = fbits16_asm_operand; 88} 89 90//===----------------------------------------------------------------------===// 91// Load / store Instructions. 92// 93 94let canFoldAsLoad = 1, isReMaterializable = 1 in { 95 96def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 97 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 99 100def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 101 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 102 [(set SPR:$Sd, (load addrmode5:$addr))]> { 103 // Some single precision VFP instructions may be executed on both NEON and VFP 104 // pipelines. 105 let D = VFPNeonDomain; 106} 107 108} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 109 110def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 111 IIC_fpStore64, "vstr", "\t$Dd, $addr", 112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 113 114def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 115 IIC_fpStore32, "vstr", "\t$Sd, $addr", 116 [(store SPR:$Sd, addrmode5:$addr)]> { 117 // Some single precision VFP instructions may be executed on both NEON and VFP 118 // pipelines. 119 let D = VFPNeonDomain; 120} 121 122//===----------------------------------------------------------------------===// 123// Load / store multiple Instructions. 124// 125 126multiclass vfp_ldst_mult<string asm, bit L_bit, 127 InstrItinClass itin, InstrItinClass itin_upd> { 128 // Double Precision 129 def DIA : 130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 131 IndexModeNone, itin, 132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 133 let Inst{24-23} = 0b01; // Increment After 134 let Inst{21} = 0; // No writeback 135 let Inst{20} = L_bit; 136 } 137 def DIA_UPD : 138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 139 variable_ops), 140 IndexModeUpd, itin_upd, 141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 142 let Inst{24-23} = 0b01; // Increment After 143 let Inst{21} = 1; // Writeback 144 let Inst{20} = L_bit; 145 } 146 def DDB_UPD : 147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 148 variable_ops), 149 IndexModeUpd, itin_upd, 150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 151 let Inst{24-23} = 0b10; // Decrement Before 152 let Inst{21} = 1; // Writeback 153 let Inst{20} = L_bit; 154 } 155 156 // Single Precision 157 def SIA : 158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 159 IndexModeNone, itin, 160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 161 let Inst{24-23} = 0b01; // Increment After 162 let Inst{21} = 0; // No writeback 163 let Inst{20} = L_bit; 164 165 // Some single precision VFP instructions may be executed on both NEON and 166 // VFP pipelines. 167 let D = VFPNeonDomain; 168 } 169 def SIA_UPD : 170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 171 variable_ops), 172 IndexModeUpd, itin_upd, 173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 174 let Inst{24-23} = 0b01; // Increment After 175 let Inst{21} = 1; // Writeback 176 let Inst{20} = L_bit; 177 178 // Some single precision VFP instructions may be executed on both NEON and 179 // VFP pipelines. 180 let D = VFPNeonDomain; 181 } 182 def SDB_UPD : 183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 184 variable_ops), 185 IndexModeUpd, itin_upd, 186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 187 let Inst{24-23} = 0b10; // Decrement Before 188 let Inst{21} = 1; // Writeback 189 let Inst{20} = L_bit; 190 191 // Some single precision VFP instructions may be executed on both NEON and 192 // VFP pipelines. 193 let D = VFPNeonDomain; 194 } 195} 196 197let neverHasSideEffects = 1 in { 198 199let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 200defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 201 202let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 203defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>; 204 205} // neverHasSideEffects 206 207def : MnemonicAlias<"vldm", "vldmia">; 208def : MnemonicAlias<"vstm", "vstmia">; 209 210def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, 211 Requires<[HasVFP2]>; 212def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, 213 Requires<[HasVFP2]>; 214def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, 215 Requires<[HasVFP2]>; 216def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, 217 Requires<[HasVFP2]>; 218defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 220defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 222defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 224defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 226 227// FLDMX, FSTMX - Load and store multiple unknown precision registers for 228// pre-armv6 cores. 229// These instruction are deprecated so we don't want them to get selected. 230multiclass vfp_ldstx_mult<string asm, bit L_bit> { 231 // Unknown precision 232 def XIA : 233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 235 let Inst{24-23} = 0b01; // Increment After 236 let Inst{21} = 0; // No writeback 237 let Inst{20} = L_bit; 238 } 239 def XIA_UPD : 240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 242 let Inst{24-23} = 0b01; // Increment After 243 let Inst{21} = 1; // Writeback 244 let Inst{20} = L_bit; 245 } 246 def XDB_UPD : 247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 249 let Inst{24-23} = 0b10; // Decrement Before 250 let Inst{21} = 1; 251 let Inst{20} = L_bit; 252 } 253} 254 255defm FLDM : vfp_ldstx_mult<"fldm", 1>; 256defm FSTM : vfp_ldstx_mult<"fstm", 0>; 257 258//===----------------------------------------------------------------------===// 259// FP Binary Operations. 260// 261 262let TwoOperandAliasConstraint = "$Dn = $Dd" in 263def VADDD : ADbI<0b11100, 0b11, 0, 0, 264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 267 268let TwoOperandAliasConstraint = "$Sn = $Sd" in 269def VADDS : ASbIn<0b11100, 0b11, 0, 0, 270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 273 // Some single precision VFP instructions may be executed on both NEON and 274 // VFP pipelines on A8. 275 let D = VFPNeonA8Domain; 276} 277 278let TwoOperandAliasConstraint = "$Dn = $Dd" in 279def VSUBD : ADbI<0b11100, 0b11, 1, 0, 280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 283 284let TwoOperandAliasConstraint = "$Sn = $Sd" in 285def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { 289 // Some single precision VFP instructions may be executed on both NEON and 290 // VFP pipelines on A8. 291 let D = VFPNeonA8Domain; 292} 293 294let TwoOperandAliasConstraint = "$Dn = $Dd" in 295def VDIVD : ADbI<0b11101, 0b00, 0, 0, 296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; 299 300let TwoOperandAliasConstraint = "$Sn = $Sd" in 301def VDIVS : ASbI<0b11101, 0b00, 0, 0, 302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; 305 306let TwoOperandAliasConstraint = "$Dn = $Dd" in 307def VMULD : ADbI<0b11100, 0b10, 0, 0, 308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; 311 312let TwoOperandAliasConstraint = "$Sn = $Sd" in 313def VMULS : ASbIn<0b11100, 0b10, 0, 0, 314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { 317 // Some single precision VFP instructions may be executed on both NEON and 318 // VFP pipelines on A8. 319 let D = VFPNeonA8Domain; 320} 321 322def VNMULD : ADbI<0b11100, 0b10, 1, 0, 323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; 326 327def VNMULS : ASbI<0b11100, 0b10, 1, 0, 328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { 331 // Some single precision VFP instructions may be executed on both NEON and 332 // VFP pipelines on A8. 333 let D = VFPNeonA8Domain; 334} 335 336multiclass vsel_inst<string op, bits<2> opc> { 337 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { 338 def S : ASbInp<0b11100, opc, 0, 339 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 340 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 341 []>, Requires<[HasV8FP]>; 342 343 def D : ADbInp<0b11100, opc, 0, 344 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 345 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 346 []>, Requires<[HasV8FP]>; 347 } 348} 349 350defm VSELGT : vsel_inst<"gt", 0b11>; 351defm VSELGE : vsel_inst<"ge", 0b10>; 352defm VSELEQ : vsel_inst<"eq", 0b00>; 353defm VSELVS : vsel_inst<"vs", 0b01>; 354 355multiclass vmaxmin_inst<string op, bit opc> { 356 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { 357 def S : ASbInp<0b11101, 0b00, opc, 358 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 359 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 360 []>, Requires<[HasV8FP]>; 361 362 def D : ADbInp<0b11101, 0b00, opc, 363 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 364 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 365 []>, Requires<[HasV8FP]>; 366 } 367} 368 369defm VMAXNM : vmaxmin_inst<"vmaxnm", 0>; 370defm VMINNM : vmaxmin_inst<"vminnm", 1>; 371 372// Match reassociated forms only if not sign dependent rounding. 373def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 374 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 375def : Pat<(fmul (fneg SPR:$a), SPR:$b), 376 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 377 378// These are encoded as unary instructions. 379let Defs = [FPSCR_NZCV] in { 380def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 381 (outs), (ins DPR:$Dd, DPR:$Dm), 382 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 383 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 384 385def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 386 (outs), (ins SPR:$Sd, SPR:$Sm), 387 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 388 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 389 // Some single precision VFP instructions may be executed on both NEON and 390 // VFP pipelines on A8. 391 let D = VFPNeonA8Domain; 392} 393 394// FIXME: Verify encoding after integrated assembler is working. 395def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 396 (outs), (ins DPR:$Dd, DPR:$Dm), 397 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 398 [/* For disassembly only; pattern left blank */]>; 399 400def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 401 (outs), (ins SPR:$Sd, SPR:$Sm), 402 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 403 [/* For disassembly only; pattern left blank */]> { 404 // Some single precision VFP instructions may be executed on both NEON and 405 // VFP pipelines on A8. 406 let D = VFPNeonA8Domain; 407} 408} // Defs = [FPSCR_NZCV] 409 410//===----------------------------------------------------------------------===// 411// FP Unary Operations. 412// 413 414def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 415 (outs DPR:$Dd), (ins DPR:$Dm), 416 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 417 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 418 419def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 420 (outs SPR:$Sd), (ins SPR:$Sm), 421 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 422 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 423 // Some single precision VFP instructions may be executed on both NEON and 424 // VFP pipelines on A8. 425 let D = VFPNeonA8Domain; 426} 427 428let Defs = [FPSCR_NZCV] in { 429def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 430 (outs), (ins DPR:$Dd), 431 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 432 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 433 let Inst{3-0} = 0b0000; 434 let Inst{5} = 0; 435} 436 437def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 438 (outs), (ins SPR:$Sd), 439 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 440 [(arm_cmpfp0 SPR:$Sd)]> { 441 let Inst{3-0} = 0b0000; 442 let Inst{5} = 0; 443 444 // Some single precision VFP instructions may be executed on both NEON and 445 // VFP pipelines on A8. 446 let D = VFPNeonA8Domain; 447} 448 449// FIXME: Verify encoding after integrated assembler is working. 450def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 451 (outs), (ins DPR:$Dd), 452 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 453 [/* For disassembly only; pattern left blank */]> { 454 let Inst{3-0} = 0b0000; 455 let Inst{5} = 0; 456} 457 458def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 459 (outs), (ins SPR:$Sd), 460 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 461 [/* For disassembly only; pattern left blank */]> { 462 let Inst{3-0} = 0b0000; 463 let Inst{5} = 0; 464 465 // Some single precision VFP instructions may be executed on both NEON and 466 // VFP pipelines on A8. 467 let D = VFPNeonA8Domain; 468} 469} // Defs = [FPSCR_NZCV] 470 471def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 472 (outs DPR:$Dd), (ins SPR:$Sm), 473 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 474 [(set DPR:$Dd, (fextend SPR:$Sm))]> { 475 // Instruction operands. 476 bits<5> Dd; 477 bits<5> Sm; 478 479 // Encode instruction operands. 480 let Inst{3-0} = Sm{4-1}; 481 let Inst{5} = Sm{0}; 482 let Inst{15-12} = Dd{3-0}; 483 let Inst{22} = Dd{4}; 484} 485 486// Special case encoding: bits 11-8 is 0b1011. 487def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 488 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 489 [(set SPR:$Sd, (fround DPR:$Dm))]> { 490 // Instruction operands. 491 bits<5> Sd; 492 bits<5> Dm; 493 494 // Encode instruction operands. 495 let Inst{3-0} = Dm{3-0}; 496 let Inst{5} = Dm{4}; 497 let Inst{15-12} = Sd{4-1}; 498 let Inst{22} = Sd{0}; 499 500 let Inst{27-23} = 0b11101; 501 let Inst{21-16} = 0b110111; 502 let Inst{11-8} = 0b1011; 503 let Inst{7-6} = 0b11; 504 let Inst{4} = 0; 505} 506 507// Between half, single and double-precision. For disassembly only. 508 509// FIXME: Verify encoding after integrated assembler is working. 510def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 511 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 512 [/* For disassembly only; pattern left blank */]>; 513 514def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 515 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 516 [/* For disassembly only; pattern left blank */]>; 517 518def : Pat<(f32_to_f16 SPR:$a), 519 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 520 521def : Pat<(f16_to_f32 GPR:$a), 522 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 523 524def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 525 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 526 [/* For disassembly only; pattern left blank */]>; 527 528def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 529 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 530 [/* For disassembly only; pattern left blank */]>; 531 532def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 533 (outs DPR:$Dd), (ins SPR:$Sm), 534 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 535 []>, Requires<[HasV8FP]> { 536 // Instruction operands. 537 bits<5> Sm; 538 539 // Encode instruction operands. 540 let Inst{3-0} = Sm{4-1}; 541 let Inst{5} = Sm{0}; 542} 543 544def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 545 (outs SPR:$Sd), (ins DPR:$Dm), 546 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 547 []>, Requires<[HasV8FP]> { 548 // Instruction operands. 549 bits<5> Sd; 550 bits<5> Dm; 551 552 // Encode instruction operands. 553 let Inst{3-0} = Dm{3-0}; 554 let Inst{5} = Dm{4}; 555 let Inst{15-12} = Sd{4-1}; 556 let Inst{22} = Sd{0}; 557} 558 559def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 560 (outs DPR:$Dd), (ins SPR:$Sm), 561 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 562 []>, Requires<[HasV8FP]> { 563 // Instruction operands. 564 bits<5> Sm; 565 566 // Encode instruction operands. 567 let Inst{3-0} = Sm{4-1}; 568 let Inst{5} = Sm{0}; 569} 570 571def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 572 (outs SPR:$Sd), (ins DPR:$Dm), 573 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 574 []>, Requires<[HasV8FP]> { 575 // Instruction operands. 576 bits<5> Sd; 577 bits<5> Dm; 578 579 // Encode instruction operands. 580 let Inst{15-12} = Sd{4-1}; 581 let Inst{22} = Sd{0}; 582 let Inst{3-0} = Dm{3-0}; 583 let Inst{5} = Dm{4}; 584} 585 586multiclass vcvt_inst<string opc, bits<2> rm> { 587 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 588 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 589 (outs SPR:$Sd), (ins SPR:$Sm), 590 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 591 []>, Requires<[HasV8FP]> { 592 let Inst{17-16} = rm; 593 } 594 595 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 596 (outs SPR:$Sd), (ins SPR:$Sm), 597 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 598 []>, Requires<[HasV8FP]> { 599 let Inst{17-16} = rm; 600 } 601 602 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 603 (outs SPR:$Sd), (ins DPR:$Dm), 604 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 605 []>, Requires<[HasV8FP]> { 606 bits<5> Dm; 607 608 let Inst{17-16} = rm; 609 610 // Encode instruction operands 611 let Inst{3-0} = Dm{3-0}; 612 let Inst{5} = Dm{4}; 613 let Inst{8} = 1; 614 } 615 616 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 617 (outs SPR:$Sd), (ins DPR:$Dm), 618 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 619 []>, Requires<[HasV8FP]> { 620 bits<5> Dm; 621 622 let Inst{17-16} = rm; 623 624 // Encode instruction operands 625 let Inst{3-0} = Dm{3-0}; 626 let Inst{5} = Dm{4}; 627 let Inst{8} = 1; 628 } 629 } 630} 631 632defm VCVTA : vcvt_inst<"a", 0b00>; 633defm VCVTN : vcvt_inst<"n", 0b01>; 634defm VCVTP : vcvt_inst<"p", 0b10>; 635defm VCVTM : vcvt_inst<"m", 0b11>; 636 637def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 638 (outs DPR:$Dd), (ins DPR:$Dm), 639 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 640 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 641 642def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 643 (outs SPR:$Sd), (ins SPR:$Sm), 644 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 645 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 646 // Some single precision VFP instructions may be executed on both NEON and 647 // VFP pipelines on A8. 648 let D = VFPNeonA8Domain; 649} 650 651multiclass vrint_inst_zrx<string opc, bit op, bit op2> { 652 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 653 (outs SPR:$Sd), (ins SPR:$Sm), 654 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 655 []>, Requires<[HasV8FP]> { 656 let Inst{7} = op2; 657 let Inst{16} = op; 658 } 659 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 660 (outs DPR:$Dd), (ins DPR:$Dm), 661 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 662 []>, Requires<[HasV8FP]> { 663 let Inst{7} = op2; 664 let Inst{16} = op; 665 } 666} 667 668defm VRINTZ : vrint_inst_zrx<"z", 0, 1>; 669defm VRINTR : vrint_inst_zrx<"r", 0, 0>; 670defm VRINTX : vrint_inst_zrx<"x", 1, 0>; 671 672multiclass vrint_inst_anpm<string opc, bits<2> rm> { 673 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 674 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 675 (outs SPR:$Sd), (ins SPR:$Sm), 676 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 677 []>, Requires<[HasV8FP]> { 678 let Inst{17-16} = rm; 679 } 680 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 681 (outs DPR:$Dd), (ins DPR:$Dm), 682 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 683 []>, Requires<[HasV8FP]> { 684 let Inst{17-16} = rm; 685 } 686 } 687 688 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 689 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>; 690 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 691 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>; 692} 693 694defm VRINTA : vrint_inst_anpm<"a", 0b00>; 695defm VRINTN : vrint_inst_anpm<"n", 0b01>; 696defm VRINTP : vrint_inst_anpm<"p", 0b10>; 697defm VRINTM : vrint_inst_anpm<"m", 0b11>; 698 699def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 700 (outs DPR:$Dd), (ins DPR:$Dm), 701 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 702 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; 703 704def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 705 (outs SPR:$Sd), (ins SPR:$Sm), 706 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 707 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; 708 709let neverHasSideEffects = 1 in { 710def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 711 (outs DPR:$Dd), (ins DPR:$Dm), 712 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; 713 714def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 715 (outs SPR:$Sd), (ins SPR:$Sm), 716 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; 717} // neverHasSideEffects 718 719//===----------------------------------------------------------------------===// 720// FP <-> GPR Copies. Int <-> FP Conversions. 721// 722 723def VMOVRS : AVConv2I<0b11100001, 0b1010, 724 (outs GPR:$Rt), (ins SPR:$Sn), 725 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 726 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { 727 // Instruction operands. 728 bits<4> Rt; 729 bits<5> Sn; 730 731 // Encode instruction operands. 732 let Inst{19-16} = Sn{4-1}; 733 let Inst{7} = Sn{0}; 734 let Inst{15-12} = Rt; 735 736 let Inst{6-5} = 0b00; 737 let Inst{3-0} = 0b0000; 738 739 // Some single precision VFP instructions may be executed on both NEON and VFP 740 // pipelines. 741 let D = VFPNeonDomain; 742} 743 744// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 745def VMOVSR : AVConv4I<0b11100000, 0b1010, 746 (outs SPR:$Sn), (ins GPR:$Rt), 747 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 748 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 749 Requires<[HasVFP2, UseVMOVSR]> { 750 // Instruction operands. 751 bits<5> Sn; 752 bits<4> Rt; 753 754 // Encode instruction operands. 755 let Inst{19-16} = Sn{4-1}; 756 let Inst{7} = Sn{0}; 757 let Inst{15-12} = Rt; 758 759 let Inst{6-5} = 0b00; 760 let Inst{3-0} = 0b0000; 761 762 // Some single precision VFP instructions may be executed on both NEON and VFP 763 // pipelines. 764 let D = VFPNeonDomain; 765} 766 767let neverHasSideEffects = 1 in { 768def VMOVRRD : AVConv3I<0b11000101, 0b1011, 769 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 770 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 771 [/* FIXME: Can't write pattern for multiple result instr*/]> { 772 // Instruction operands. 773 bits<5> Dm; 774 bits<4> Rt; 775 bits<4> Rt2; 776 777 // Encode instruction operands. 778 let Inst{3-0} = Dm{3-0}; 779 let Inst{5} = Dm{4}; 780 let Inst{15-12} = Rt; 781 let Inst{19-16} = Rt2; 782 783 let Inst{7-6} = 0b00; 784 785 // Some single precision VFP instructions may be executed on both NEON and VFP 786 // pipelines. 787 let D = VFPNeonDomain; 788} 789 790def VMOVRRS : AVConv3I<0b11000101, 0b1010, 791 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 792 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 793 [/* For disassembly only; pattern left blank */]> { 794 bits<5> src1; 795 bits<4> Rt; 796 bits<4> Rt2; 797 798 // Encode instruction operands. 799 let Inst{3-0} = src1{4-1}; 800 let Inst{5} = src1{0}; 801 let Inst{15-12} = Rt; 802 let Inst{19-16} = Rt2; 803 804 let Inst{7-6} = 0b00; 805 806 // Some single precision VFP instructions may be executed on both NEON and VFP 807 // pipelines. 808 let D = VFPNeonDomain; 809 let DecoderMethod = "DecodeVMOVRRS"; 810} 811} // neverHasSideEffects 812 813// FMDHR: GPR -> SPR 814// FMDLR: GPR -> SPR 815 816def VMOVDRR : AVConv5I<0b11000100, 0b1011, 817 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 818 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 819 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { 820 // Instruction operands. 821 bits<5> Dm; 822 bits<4> Rt; 823 bits<4> Rt2; 824 825 // Encode instruction operands. 826 let Inst{3-0} = Dm{3-0}; 827 let Inst{5} = Dm{4}; 828 let Inst{15-12} = Rt; 829 let Inst{19-16} = Rt2; 830 831 let Inst{7-6} = 0b00; 832 833 // Some single precision VFP instructions may be executed on both NEON and VFP 834 // pipelines. 835 let D = VFPNeonDomain; 836} 837 838let neverHasSideEffects = 1 in 839def VMOVSRR : AVConv5I<0b11000100, 0b1010, 840 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 841 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 842 [/* For disassembly only; pattern left blank */]> { 843 // Instruction operands. 844 bits<5> dst1; 845 bits<4> src1; 846 bits<4> src2; 847 848 // Encode instruction operands. 849 let Inst{3-0} = dst1{4-1}; 850 let Inst{5} = dst1{0}; 851 let Inst{15-12} = src1; 852 let Inst{19-16} = src2; 853 854 let Inst{7-6} = 0b00; 855 856 // Some single precision VFP instructions may be executed on both NEON and VFP 857 // pipelines. 858 let D = VFPNeonDomain; 859 860 let DecoderMethod = "DecodeVMOVSRR"; 861} 862 863// FMRDH: SPR -> GPR 864// FMRDL: SPR -> GPR 865// FMRRS: SPR -> GPR 866// FMRX: SPR system reg -> GPR 867// FMSRR: GPR -> SPR 868// FMXR: GPR -> VFP system reg 869 870 871// Int -> FP: 872 873class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 874 bits<4> opcod4, dag oops, dag iops, 875 InstrItinClass itin, string opc, string asm, 876 list<dag> pattern> 877 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 878 pattern> { 879 // Instruction operands. 880 bits<5> Dd; 881 bits<5> Sm; 882 883 // Encode instruction operands. 884 let Inst{3-0} = Sm{4-1}; 885 let Inst{5} = Sm{0}; 886 let Inst{15-12} = Dd{3-0}; 887 let Inst{22} = Dd{4}; 888} 889 890class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 891 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 892 string opc, string asm, list<dag> pattern> 893 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 894 pattern> { 895 // Instruction operands. 896 bits<5> Sd; 897 bits<5> Sm; 898 899 // Encode instruction operands. 900 let Inst{3-0} = Sm{4-1}; 901 let Inst{5} = Sm{0}; 902 let Inst{15-12} = Sd{4-1}; 903 let Inst{22} = Sd{0}; 904} 905 906def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 907 (outs DPR:$Dd), (ins SPR:$Sm), 908 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 909 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { 910 let Inst{7} = 1; // s32 911} 912 913def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 914 (outs SPR:$Sd),(ins SPR:$Sm), 915 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 916 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { 917 let Inst{7} = 1; // s32 918 919 // Some single precision VFP instructions may be executed on both NEON and 920 // VFP pipelines on A8. 921 let D = VFPNeonA8Domain; 922} 923 924def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 925 (outs DPR:$Dd), (ins SPR:$Sm), 926 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 927 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { 928 let Inst{7} = 0; // u32 929} 930 931def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 932 (outs SPR:$Sd), (ins SPR:$Sm), 933 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 934 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { 935 let Inst{7} = 0; // u32 936 937 // Some single precision VFP instructions may be executed on both NEON and 938 // VFP pipelines on A8. 939 let D = VFPNeonA8Domain; 940} 941 942// FP -> Int: 943 944class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 945 bits<4> opcod4, dag oops, dag iops, 946 InstrItinClass itin, string opc, string asm, 947 list<dag> pattern> 948 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 949 pattern> { 950 // Instruction operands. 951 bits<5> Sd; 952 bits<5> Dm; 953 954 // Encode instruction operands. 955 let Inst{3-0} = Dm{3-0}; 956 let Inst{5} = Dm{4}; 957 let Inst{15-12} = Sd{4-1}; 958 let Inst{22} = Sd{0}; 959} 960 961class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 962 bits<4> opcod4, dag oops, dag iops, 963 InstrItinClass itin, string opc, string asm, 964 list<dag> pattern> 965 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 966 pattern> { 967 // Instruction operands. 968 bits<5> Sd; 969 bits<5> Sm; 970 971 // Encode instruction operands. 972 let Inst{3-0} = Sm{4-1}; 973 let Inst{5} = Sm{0}; 974 let Inst{15-12} = Sd{4-1}; 975 let Inst{22} = Sd{0}; 976} 977 978// Always set Z bit in the instruction, i.e. "round towards zero" variants. 979def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 980 (outs SPR:$Sd), (ins DPR:$Dm), 981 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 982 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { 983 let Inst{7} = 1; // Z bit 984} 985 986def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 987 (outs SPR:$Sd), (ins SPR:$Sm), 988 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 989 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { 990 let Inst{7} = 1; // Z bit 991 992 // Some single precision VFP instructions may be executed on both NEON and 993 // VFP pipelines on A8. 994 let D = VFPNeonA8Domain; 995} 996 997def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 998 (outs SPR:$Sd), (ins DPR:$Dm), 999 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1000 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { 1001 let Inst{7} = 1; // Z bit 1002} 1003 1004def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1005 (outs SPR:$Sd), (ins SPR:$Sm), 1006 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1007 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { 1008 let Inst{7} = 1; // Z bit 1009 1010 // Some single precision VFP instructions may be executed on both NEON and 1011 // VFP pipelines on A8. 1012 let D = VFPNeonA8Domain; 1013} 1014 1015// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1016let Uses = [FPSCR] in { 1017// FIXME: Verify encoding after integrated assembler is working. 1018def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1019 (outs SPR:$Sd), (ins DPR:$Dm), 1020 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1021 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ 1022 let Inst{7} = 0; // Z bit 1023} 1024 1025def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1026 (outs SPR:$Sd), (ins SPR:$Sm), 1027 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1028 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { 1029 let Inst{7} = 0; // Z bit 1030} 1031 1032def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1033 (outs SPR:$Sd), (ins DPR:$Dm), 1034 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1035 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ 1036 let Inst{7} = 0; // Z bit 1037} 1038 1039def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1040 (outs SPR:$Sd), (ins SPR:$Sm), 1041 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1042 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { 1043 let Inst{7} = 0; // Z bit 1044} 1045} 1046 1047// Convert between floating-point and fixed-point 1048// Data type for fixed-point naming convention: 1049// S16 (U=0, sx=0) -> SH 1050// U16 (U=1, sx=0) -> UH 1051// S32 (U=0, sx=1) -> SL 1052// U32 (U=1, sx=1) -> UL 1053 1054let Constraints = "$a = $dst" in { 1055 1056// FP to Fixed-Point: 1057 1058// Single Precision register 1059class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1060 bit op5, dag oops, dag iops, InstrItinClass itin, 1061 string opc, string asm, list<dag> pattern> 1062 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1063 Sched<[WriteCvtFP]> { 1064 bits<5> dst; 1065 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1066 let Inst{22} = dst{0}; 1067 let Inst{15-12} = dst{4-1}; 1068} 1069 1070// Double Precision register 1071class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1072 bit op5, dag oops, dag iops, InstrItinClass itin, 1073 string opc, string asm, list<dag> pattern> 1074 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1075 Sched<[WriteCvtFP]> { 1076 bits<5> dst; 1077 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1078 let Inst{22} = dst{4}; 1079 let Inst{15-12} = dst{3-0}; 1080} 1081 1082def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1083 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1084 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> { 1085 // Some single precision VFP instructions may be executed on both NEON and 1086 // VFP pipelines on A8. 1087 let D = VFPNeonA8Domain; 1088} 1089 1090def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1091 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1092 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> { 1093 // Some single precision VFP instructions may be executed on both NEON and 1094 // VFP pipelines on A8. 1095 let D = VFPNeonA8Domain; 1096} 1097 1098def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1099 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1100 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> { 1101 // Some single precision VFP instructions may be executed on both NEON and 1102 // VFP pipelines on A8. 1103 let D = VFPNeonA8Domain; 1104} 1105 1106def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1107 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1108 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> { 1109 // Some single precision VFP instructions may be executed on both NEON and 1110 // VFP pipelines on A8. 1111 let D = VFPNeonA8Domain; 1112} 1113 1114def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1115 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1116 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>; 1117 1118def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1119 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1120 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>; 1121 1122def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1123 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1124 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>; 1125 1126def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1127 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1128 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>; 1129 1130// Fixed-Point to FP: 1131 1132def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1133 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1134 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> { 1135 // Some single precision VFP instructions may be executed on both NEON and 1136 // VFP pipelines on A8. 1137 let D = VFPNeonA8Domain; 1138} 1139 1140def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1141 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1142 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> { 1143 // Some single precision VFP instructions may be executed on both NEON and 1144 // VFP pipelines on A8. 1145 let D = VFPNeonA8Domain; 1146} 1147 1148def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1149 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1150 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> { 1151 // Some single precision VFP instructions may be executed on both NEON and 1152 // VFP pipelines on A8. 1153 let D = VFPNeonA8Domain; 1154} 1155 1156def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1157 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1158 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> { 1159 // Some single precision VFP instructions may be executed on both NEON and 1160 // VFP pipelines on A8. 1161 let D = VFPNeonA8Domain; 1162} 1163 1164def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1165 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1166 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>; 1167 1168def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1169 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1170 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>; 1171 1172def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1173 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1174 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>; 1175 1176def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1177 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1178 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>; 1179 1180} // End of 'let Constraints = "$a = $dst" in' 1181 1182//===----------------------------------------------------------------------===// 1183// FP Multiply-Accumulate Operations. 1184// 1185 1186def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1187 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1188 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1189 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1190 (f64 DPR:$Ddin)))]>, 1191 RegConstraint<"$Ddin = $Dd">, 1192 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1193 1194def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 1195 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1196 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 1197 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1198 SPR:$Sdin))]>, 1199 RegConstraint<"$Sdin = $Sd">, 1200 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1201 // Some single precision VFP instructions may be executed on both NEON and 1202 // VFP pipelines on A8. 1203 let D = VFPNeonA8Domain; 1204} 1205 1206def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1207 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1208 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1209def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1210 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1211 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>; 1212 1213def VMLSD : ADbI<0b11100, 0b00, 1, 0, 1214 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1215 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 1216 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1217 (f64 DPR:$Ddin)))]>, 1218 RegConstraint<"$Ddin = $Dd">, 1219 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1220 1221def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1222 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1223 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1224 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1225 SPR:$Sdin))]>, 1226 RegConstraint<"$Sdin = $Sd">, 1227 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1228 // Some single precision VFP instructions may be executed on both NEON and 1229 // VFP pipelines on A8. 1230 let D = VFPNeonA8Domain; 1231} 1232 1233def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1234 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1235 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1236def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1237 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1238 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1239 1240def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1241 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1242 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1243 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1244 (f64 DPR:$Ddin)))]>, 1245 RegConstraint<"$Ddin = $Dd">, 1246 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1247 1248def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1249 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1250 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1251 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1252 SPR:$Sdin))]>, 1253 RegConstraint<"$Sdin = $Sd">, 1254 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1255 // Some single precision VFP instructions may be executed on both NEON and 1256 // VFP pipelines on A8. 1257 let D = VFPNeonA8Domain; 1258} 1259 1260def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1261 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1262 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1263def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1264 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1265 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1266 1267def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 1268 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1269 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 1270 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1271 (f64 DPR:$Ddin)))]>, 1272 RegConstraint<"$Ddin = $Dd">, 1273 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1274 1275def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 1276 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1277 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 1278 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1279 RegConstraint<"$Sdin = $Sd">, 1280 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1281 // Some single precision VFP instructions may be executed on both NEON and 1282 // VFP pipelines on A8. 1283 let D = VFPNeonA8Domain; 1284} 1285 1286def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1287 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1288 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>; 1289def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1290 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1291 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1292 1293//===----------------------------------------------------------------------===// 1294// Fused FP Multiply-Accumulate Operations. 1295// 1296def VFMAD : ADbI<0b11101, 0b10, 0, 0, 1297 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1298 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 1299 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1300 (f64 DPR:$Ddin)))]>, 1301 RegConstraint<"$Ddin = $Dd">, 1302 Requires<[HasVFP4,UseFusedMAC]>; 1303 1304def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 1305 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1306 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 1307 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1308 SPR:$Sdin))]>, 1309 RegConstraint<"$Sdin = $Sd">, 1310 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1311 // Some single precision VFP instructions may be executed on both NEON and 1312 // VFP pipelines. 1313} 1314 1315def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1316 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1317 Requires<[HasVFP4,UseFusedMAC]>; 1318def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1319 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1320 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1321 1322// Match @llvm.fma.* intrinsics 1323// (fma x, y, z) -> (vfms z, x, y) 1324def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 1325 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1326 Requires<[HasVFP4]>; 1327def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 1328 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1329 Requires<[HasVFP4]>; 1330 1331def VFMSD : ADbI<0b11101, 0b10, 1, 0, 1332 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1333 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 1334 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1335 (f64 DPR:$Ddin)))]>, 1336 RegConstraint<"$Ddin = $Dd">, 1337 Requires<[HasVFP4,UseFusedMAC]>; 1338 1339def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 1340 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1341 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 1342 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1343 SPR:$Sdin))]>, 1344 RegConstraint<"$Sdin = $Sd">, 1345 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1346 // Some single precision VFP instructions may be executed on both NEON and 1347 // VFP pipelines. 1348} 1349 1350def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1351 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1352 Requires<[HasVFP4,UseFusedMAC]>; 1353def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1354 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1355 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1356 1357// Match @llvm.fma.* intrinsics 1358// (fma (fneg x), y, z) -> (vfms z, x, y) 1359def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 1360 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1361 Requires<[HasVFP4]>; 1362def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 1363 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1364 Requires<[HasVFP4]>; 1365// (fma x, (fneg y), z) -> (vfms z, x, y) 1366def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 1367 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1368 Requires<[HasVFP4]>; 1369def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 1370 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1371 Requires<[HasVFP4]>; 1372 1373def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 1374 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1375 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 1376 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1377 (f64 DPR:$Ddin)))]>, 1378 RegConstraint<"$Ddin = $Dd">, 1379 Requires<[HasVFP4,UseFusedMAC]>; 1380 1381def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 1382 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1383 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 1384 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1385 SPR:$Sdin))]>, 1386 RegConstraint<"$Sdin = $Sd">, 1387 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1388 // Some single precision VFP instructions may be executed on both NEON and 1389 // VFP pipelines. 1390} 1391 1392def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1393 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1394 Requires<[HasVFP4,UseFusedMAC]>; 1395def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1396 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1397 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1398 1399// Match @llvm.fma.* intrinsics 1400// (fneg (fma x, y, z)) -> (vfnma z, x, y) 1401def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 1402 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1403 Requires<[HasVFP4]>; 1404def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 1405 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1406 Requires<[HasVFP4]>; 1407// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 1408def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 1409 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1410 Requires<[HasVFP4]>; 1411def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 1412 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1413 Requires<[HasVFP4]>; 1414 1415def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 1416 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1417 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 1418 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1419 (f64 DPR:$Ddin)))]>, 1420 RegConstraint<"$Ddin = $Dd">, 1421 Requires<[HasVFP4,UseFusedMAC]>; 1422 1423def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 1424 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1425 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 1426 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1427 RegConstraint<"$Sdin = $Sd">, 1428 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1429 // Some single precision VFP instructions may be executed on both NEON and 1430 // VFP pipelines. 1431} 1432 1433def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1434 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1435 Requires<[HasVFP4,UseFusedMAC]>; 1436def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1437 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1438 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1439 1440// Match @llvm.fma.* intrinsics 1441 1442// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 1443def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 1444 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1445 Requires<[HasVFP4]>; 1446def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 1447 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1448 Requires<[HasVFP4]>; 1449// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 1450def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 1451 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1452 Requires<[HasVFP4]>; 1453def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 1454 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1455 Requires<[HasVFP4]>; 1456// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 1457def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 1458 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1459 Requires<[HasVFP4]>; 1460def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 1461 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1462 Requires<[HasVFP4]>; 1463 1464//===----------------------------------------------------------------------===// 1465// FP Conditional moves. 1466// 1467 1468let neverHasSideEffects = 1 in { 1469def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p), 1470 4, IIC_fpUNA64, 1471 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>, 1472 RegConstraint<"$Dn = $Dd">; 1473 1474def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p), 1475 4, IIC_fpUNA32, 1476 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>, 1477 RegConstraint<"$Sn = $Sd">; 1478} // neverHasSideEffects 1479 1480//===----------------------------------------------------------------------===// 1481// Move from VFP System Register to ARM core register. 1482// 1483 1484class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1485 list<dag> pattern>: 1486 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1487 1488 // Instruction operand. 1489 bits<4> Rt; 1490 1491 let Inst{27-20} = 0b11101111; 1492 let Inst{19-16} = opc19_16; 1493 let Inst{15-12} = Rt; 1494 let Inst{11-8} = 0b1010; 1495 let Inst{7} = 0; 1496 let Inst{6-5} = 0b00; 1497 let Inst{4} = 1; 1498 let Inst{3-0} = 0b0000; 1499} 1500 1501// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1502// to APSR. 1503let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in 1504def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 1505 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 1506 1507// Application level FPSCR -> GPR 1508let hasSideEffects = 1, Uses = [FPSCR] in 1509def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), 1510 "vmrs", "\t$Rt, fpscr", 1511 [(set GPR:$Rt, (int_arm_get_fpscr))]>; 1512 1513// System level FPEXC, FPSID -> GPR 1514let Uses = [FPSCR] in { 1515 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), 1516 "vmrs", "\t$Rt, fpexc", []>; 1517 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), 1518 "vmrs", "\t$Rt, fpsid", []>; 1519 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), 1520 "vmrs", "\t$Rt, mvfr0", []>; 1521 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), 1522 "vmrs", "\t$Rt, mvfr1", []>; 1523 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), 1524 "vmrs", "\t$Rt, fpinst", []>; 1525 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), 1526 "vmrs", "\t$Rt, fpinst2", []>; 1527} 1528 1529//===----------------------------------------------------------------------===// 1530// Move from ARM core register to VFP System Register. 1531// 1532 1533class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1534 list<dag> pattern>: 1535 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1536 1537 // Instruction operand. 1538 bits<4> src; 1539 1540 // Encode instruction operand. 1541 let Inst{15-12} = src; 1542 1543 let Inst{27-20} = 0b11101110; 1544 let Inst{19-16} = opc19_16; 1545 let Inst{11-8} = 0b1010; 1546 let Inst{7} = 0; 1547 let Inst{4} = 1; 1548} 1549 1550let Defs = [FPSCR] in { 1551 // Application level GPR -> FPSCR 1552 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), 1553 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; 1554 // System level GPR -> FPEXC 1555 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), 1556 "vmsr", "\tfpexc, $src", []>; 1557 // System level GPR -> FPSID 1558 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), 1559 "vmsr", "\tfpsid, $src", []>; 1560 1561 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src), 1562 "vmsr", "\tfpinst, $src", []>; 1563 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src), 1564 "vmsr", "\tfpinst2, $src", []>; 1565} 1566 1567//===----------------------------------------------------------------------===// 1568// Misc. 1569// 1570 1571// Materialize FP immediates. VFP3 only. 1572let isReMaterializable = 1 in { 1573def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 1574 VFPMiscFrm, IIC_fpUNA64, 1575 "vmov", ".f64\t$Dd, $imm", 1576 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> { 1577 bits<5> Dd; 1578 bits<8> imm; 1579 1580 let Inst{27-23} = 0b11101; 1581 let Inst{22} = Dd{4}; 1582 let Inst{21-20} = 0b11; 1583 let Inst{19-16} = imm{7-4}; 1584 let Inst{15-12} = Dd{3-0}; 1585 let Inst{11-9} = 0b101; 1586 let Inst{8} = 1; // Double precision. 1587 let Inst{7-4} = 0b0000; 1588 let Inst{3-0} = imm{3-0}; 1589} 1590 1591def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 1592 VFPMiscFrm, IIC_fpUNA32, 1593 "vmov", ".f32\t$Sd, $imm", 1594 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 1595 bits<5> Sd; 1596 bits<8> imm; 1597 1598 let Inst{27-23} = 0b11101; 1599 let Inst{22} = Sd{0}; 1600 let Inst{21-20} = 0b11; 1601 let Inst{19-16} = imm{7-4}; 1602 let Inst{15-12} = Sd{4-1}; 1603 let Inst{11-9} = 0b101; 1604 let Inst{8} = 0; // Single precision. 1605 let Inst{7-4} = 0b0000; 1606 let Inst{3-0} = imm{3-0}; 1607} 1608} 1609 1610//===----------------------------------------------------------------------===// 1611// Assembler aliases. 1612// 1613// A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to 1614// support them all, but supporting at least some of the basics is 1615// good to be friendly. 1616def : VFP2MnemonicAlias<"flds", "vldr">; 1617def : VFP2MnemonicAlias<"fldd", "vldr">; 1618def : VFP2MnemonicAlias<"fmrs", "vmov">; 1619def : VFP2MnemonicAlias<"fmsr", "vmov">; 1620def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 1621def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 1622def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 1623def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 1624def : VFP2MnemonicAlias<"fmrdd", "vmov">; 1625def : VFP2MnemonicAlias<"fmrds", "vmov">; 1626def : VFP2MnemonicAlias<"fmrrd", "vmov">; 1627def : VFP2MnemonicAlias<"fmdrr", "vmov">; 1628def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 1629def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 1630def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 1631def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 1632def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 1633def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 1634def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 1635def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 1636def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 1637def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 1638def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 1639def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 1640def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 1641def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 1642def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 1643def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 1644def : VFP2MnemonicAlias<"fsts", "vstr">; 1645def : VFP2MnemonicAlias<"fstd", "vstr">; 1646def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 1647def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 1648def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 1649def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 1650def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 1651def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 1652def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 1653def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 1654def : VFP2MnemonicAlias<"fmrx", "vmrs">; 1655def : VFP2MnemonicAlias<"fmxr", "vmsr">; 1656 1657// Be friendly and accept the old form of zero-compare 1658def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 1659def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 1660 1661 1662def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; 1663def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 1664 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1665def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm", 1666 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1667def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 1668 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1669def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm", 1670 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1671 1672// No need for the size suffix on VSQRT. It's implied by the register classes. 1673def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 1674def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 1675 1676// VLDR/VSTR accept an optional type suffix. 1677def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 1678 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1679def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 1680 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1681def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 1682 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1683def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 1684 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1685 1686// VMOV can accept optional 32-bit or less data type suffix suffix. 1687def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 1688 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1689def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 1690 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1691def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 1692 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1693def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 1694 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1695def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 1696 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1697def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 1698 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1699 1700def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 1701 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 1702def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 1703 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 1704 1705// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 1706// VMOVD does. 1707def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 1708 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 1709