| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
124 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument
125 return Imm & 0xFF; in getSOImmValImm()
129 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument
130 return (Imm >> 8) * 2; in getSOImmValRot()
137 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
140 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
143 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
150 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
43 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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| D | MipsAnalyzeImmediate.h | 28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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| D | Mips16InstrInfo.h | 87 int64_t Imm, MachineBasicBlock &MBB,
92 int64_t Imm, MachineBasicBlock &MBB,
106 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
109 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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| D | Mips16InstrInfo.cpp | 310 int64_t Imm, MachineBasicBlock &MBB, in loadImmediate() argument
326 int32_t lo = Imm & 0xFFFF; in loadImmediate()
391 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm); in loadImmediate()
429 int64_t Imm, MachineBasicBlock &MBB, in basicLoadImmediate() argument
435 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm); in basicLoadImmediate()
459 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { in AddiuSpImm()
460 if (validSpImm8(Imm)) in AddiuSpImm()
467 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const { in BuildAddiuSpImm()
469 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); in BuildAddiuSpImm()
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 86 IntFloatUnion Imm; in getLitEncoding() local
88 Imm.I = MO.getImm(); in getLitEncoding()
90 Imm.F = MO.getFPImm(); in getLitEncoding()
94 if (Imm.I >= 0 && Imm.I <= 64) in getLitEncoding()
95 return 128 + Imm.I; in getLitEncoding()
97 if (Imm.I >= -16 && Imm.I <= -1) in getLitEncoding()
98 return 192 + abs(Imm.I); in getLitEncoding()
100 if (Imm.F == 0.5f) in getLitEncoding()
103 if (Imm.F == -0.5f) in getLitEncoding()
106 if (Imm.F == 1.0f) in getLitEncoding()
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| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument
31 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
32 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
33 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
64 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask() argument
67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); in DecodePALIGNRMask()
85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask() argument
91 unsigned NewImm = Imm; in DecodePSHUFMask()
97 if (NumLaneElts == 4) NewImm = Imm; // reload imm in DecodePSHUFMask()
101 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask() argument
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| D | X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
44 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
67 void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 106 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
107 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeUImmOperand()
108 Inst.addOperand(MCOperand::CreateImm(Imm)); in decodeUImmOperand()
113 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
114 assert(isUInt<N>(Imm) && "Invalid immediate"); in decodeSImmOperand()
115 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
119 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, in decodeAccessRegOperand() argument
122 return decodeUImmOperand<4>(Inst, Imm); in decodeAccessRegOperand()
125 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU4ImmOperand() argument
127 return decodeUImmOperand<4>(Inst, Imm); in decodeU4ImmOperand()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 97 unsigned PPCMaterialize32BitInt(int64_t Imm,
99 unsigned PPCMaterialize64BitInt(int64_t Imm,
156 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm, in PPCMaterialize32BitInt() argument
158 unsigned Lo = Imm & 0xFFFF; in PPCMaterialize32BitInt()
159 unsigned Hi = (Imm >> 16) & 0xFFFF; in PPCMaterialize32BitInt()
164 if (isInt<16>(Imm)) in PPCMaterialize32BitInt()
167 .addImm(Imm); in PPCMaterialize32BitInt()
188 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm, in PPCMaterialize64BitInt() argument
195 if (!isInt<32>(Imm)) { in PPCMaterialize64BitInt()
196 Shift = countTrailingZeros<uint64_t>(Imm); in PPCMaterialize64BitInt()
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| D | PPCISelDAGToDAG.cpp | 74 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm() argument
75 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
80 inline SDValue getI64Imm(uint64_t Imm) { in getI64Imm() argument
81 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
85 inline SDValue getSmallIPtrImm(unsigned Imm) { in getSmallIPtrImm() argument
86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); in getSmallIPtrImm()
281 static bool isIntS16Immediate(SDNode *N, short &Imm) { in isIntS16Immediate() argument
285 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
287 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
289 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
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| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| D | NVPTXInstPrinter.cpp | 97 int64_t Imm = MO.getImm(); in printCvtMode() local
101 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
105 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
109 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
147 int64_t Imm = MO.getImm(); in printCmpMode() local
151 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
154 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode()
221 int Imm = (int) MO.getImm(); in printLdStCode() local
223 if (Imm) in printLdStCode()
226 switch (Imm) { in printLdStCode()
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| /external/llvm/lib/IR/ |
| D | AutoUpgrade.cpp | 237 unsigned Imm; in UpgradeIntrinsicCall() local
239 Imm = 0; in UpgradeIntrinsicCall()
241 Imm = 1; in UpgradeIntrinsicCall()
243 Imm = 2; in UpgradeIntrinsicCall()
245 Imm = 3; in UpgradeIntrinsicCall()
247 Imm = 4; in UpgradeIntrinsicCall()
249 Imm = 5; in UpgradeIntrinsicCall()
251 Imm = 6; in UpgradeIntrinsicCall()
253 Imm = 7; in UpgradeIntrinsicCall()
259 CI->getArgOperand(1), Builder.getInt8(Imm)); in UpgradeIntrinsicCall()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 56 int32_t Imm = unpackSignedImm(9, MOImm.getImm()); in printOffsetSImm9Operand() local
58 O << '#' << Imm; in printOffsetSImm9Operand()
247 uint32_t Imm = MOImm.getImm() * MemSize; in printOffsetUImm12Operand() local
249 O << "#" << Imm; in printOffsetUImm12Operand()
366 int32_t Imm = unpackSignedImm(7, MOImm.getImm()); in printSImm7ScaledOperand() local
368 O << "#" << (Imm * MemScale); in printSImm7ScaledOperand()
425 int64_t Imm = MO.getImm(); in printNeonMovImmShiftOperand() local
428 if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1) in printNeonMovImmShiftOperand()
432 if (IsLSL && (Imm < 0 || Imm > 3)) in printNeonMovImmShiftOperand()
438 Imm++; in printNeonMovImmShiftOperand()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrNEON.td | 21 // (outs Result), (ins Imm, OpCmode)
28 // (outs Result), (ins Imm)
640 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
649 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
650 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
652 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
656 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
657 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
659 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
663 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 208 uint64_t Imm);
227 uint64_t Imm);
237 uint64_t Imm, MVT ImmType);
244 uint64_t Imm);
285 uint64_t Imm);
306 uint64_t Imm);
320 uint64_t Imm);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 406 uint64_t Imm = CI->getZExtValue(); in SelectBinaryOp() local
411 isPowerOf2_64(Imm)) { in SelectBinaryOp()
412 Imm = Log2_64(Imm); in SelectBinaryOp()
418 isPowerOf2_64(Imm)) { in SelectBinaryOp()
419 --Imm; in SelectBinaryOp()
424 Op0IsKill, Imm, VT.getSimpleVT()); in SelectBinaryOp()
1170 uint64_t Imm, MVT ImmType) { in FastEmit_ri_() argument
1172 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) { in FastEmit_ri_()
1174 Imm = Log2_64(Imm); in FastEmit_ri_()
1175 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { in FastEmit_ri_()
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| /external/llvm/lib/MC/ |
| D | MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm(); in evaluateBranch() local
20 Target = Addr+Size+Imm; in evaluateBranch()
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| /external/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 99 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const { in isLegalAddImmediate()
100 return PrevTTI->isLegalAddImmediate(Imm); in isLegalAddImmediate()
103 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const { in isLegalICmpImmediate()
104 return PrevTTI->isLegalICmpImmediate(Imm); in isLegalICmpImmediate()
148 unsigned TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const { in getIntImmCost() argument
149 return PrevTTI->getIntImmCost(Imm, Ty); in getIntImmCost()
460 bool isLegalAddImmediate(int64_t Imm) const { in isLegalAddImmediate()
464 bool isLegalICmpImmediate(int64_t Imm) const { in isLegalICmpImmediate()
508 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const { in getIntImmCost()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86IntelInstPrinter.cpp | 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; in printSSECC() local
55 switch (Imm) { in printSSECC()
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; in printAVXCC() local
79 switch (Imm) { in printAVXCC()
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| D | X86ATTInstPrinter.cpp | 64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; in printSSECC() local
65 switch (Imm) { in printSSECC()
88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; in printAVXCC() local
89 switch (Imm) { in printAVXCC()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 570 unsigned Imm = MO.getImm(); in printPostIdxImm8Operand() local
572 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff) in printPostIdxImm8Operand()
589 unsigned Imm = MO.getImm(); in printPostIdxImm8s4Operand() local
591 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2) in printPostIdxImm8s4Operand()
709 unsigned Imm = MI->getOperand(OpNum).getImm(); in printPKHLSLShiftImm() local
710 if (Imm == 0) in printPKHLSLShiftImm()
712 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); in printPKHLSLShiftImm()
713 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">"); in printPKHLSLShiftImm()
718 unsigned Imm = MI->getOperand(OpNum).getImm(); in printPKHASRShiftImm() local
720 if (Imm == 0) in printPKHASRShiftImm()
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| /external/llvm/utils/TableGen/ |
| D | PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg }; enumerator
31 uint64_t Imm; // Integer immedate value. member
104 OperandMap[BaseIdx + i].Kind = OpData::Imm; in addDagOperandMapping()
105 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); in addDagOperandMapping()
235 case OpData::Imm: in emitLoweringEmitter()
237 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; in emitLoweringEmitter()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 122 uint64_t Imm);
131 uint64_t Imm);
134 uint64_t Imm);
372 uint64_t Imm) { in FastEmitInst_ri() argument
379 .addImm(Imm)); in FastEmitInst_ri()
383 .addImm(Imm)); in FastEmitInst_ri()
417 uint64_t Imm) { in FastEmitInst_rri() argument
425 .addImm(Imm)); in FastEmitInst_rri()
430 .addImm(Imm)); in FastEmitInst_rri()
440 uint64_t Imm) { in FastEmitInst_i() argument
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| /external/llvm/lib/Target/R600/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 50 unsigned Imm = MI->getOperand(OpNum).getImm(); in printInterpSlot() local
52 if (Imm == 2) { in printInterpSlot()
54 } else if (Imm == 1) { in printInterpSlot()
56 } else if (Imm == 0) { in printInterpSlot()
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