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Searched refs:ImplicitDefs (Results 1 – 13 of 13) sorted by relevance

/external/llvm/include/llvm/MC/
DMCInstrDesc.h146 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr variable
505 return ImplicitDefs; in getImplicitDefs()
510 if (ImplicitDefs == 0) return 0; in getNumImplicitDefs()
512 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
529 if (const uint16_t *ImpDefs = ImplicitDefs)
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1232 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_r()
1254 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rr()
1278 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrr()
1299 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ri()
1322 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rii()
1343 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rf()
1367 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rri()
1391 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrii()
1407 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_i()
1424 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ii()
DScheduleDAGFast.cpp436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
514 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
DScheduleDAGSDNodes.cpp125 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
DScheduleDAGRRList.cpp1193 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1319 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp328 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
346 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
349 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h215 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp811 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
936 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
DCodeGenDAGPatterns.cpp1634 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp317 .addReg(II.ImplicitDefs[0])); in FastEmitInst_r()
339 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rr()
364 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rrr()
386 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ri()
408 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rf()
433 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rri()
452 .addReg(II.ImplicitDefs[0])); in FastEmitInst_i()
472 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ii()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp521 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp1329 if (NewDesc.ImplicitDefs) in optimizeCompareInstr()
/external/llvm/docs/
DCodeGenerator.rst1278 ``TargetInstrInfo::get(opcode)::ImplicitDefs``, where ``opcode`` is the opcode