| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); in runOnMachineFunction()
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); in runOnMachineFunction()
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); in runOnMachineFunction()
115 AddLiveIn(&MF, MRI, new_reg, virt_reg); in runOnMachineFunction()
123 MachineRegisterInfo & MRI, in AddLiveIn() argument
127 if (!MRI.isLiveIn(physReg)) { in AddLiveIn()
128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg)); in AddLiveIn()
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| D | SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); in runOnMachineFunction()
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); in runOnMachineFunction()
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); in runOnMachineFunction()
115 AddLiveIn(&MF, MRI, new_reg, virt_reg); in runOnMachineFunction()
123 MachineRegisterInfo & MRI, in AddLiveIn() argument
127 if (!MRI.isLiveIn(physReg)) { in AddLiveIn()
128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg)); in AddLiveIn()
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| D | SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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| /external/llvm/lib/Target/R600/ |
| D | SIFixSGPRCopies.cpp | 83 const MachineRegisterInfo &MRI,
110 const MachineRegisterInfo &MRI, in inferRegClass() argument
117 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in inferRegClass()
118 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), in inferRegClass()
119 E = MRI.use_end(); I != E; ++I) { in inferRegClass()
122 RC = TRI->getCommonSubClass(RC, inferRegClass(TRI, MRI, in inferRegClass()
132 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg); in runOnMachineFunction()
147 MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass); in runOnMachineFunction()
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| D | R600OptimizeVectorRegisters.cpp | 48 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { in isImplicitlyDef() argument
49 for (MachineRegisterInfo::def_iterator It = MRI.def_begin(Reg), in isImplicitlyDef()
50 E = MRI.def_end(); It != E; ++It) { in isImplicitlyDef()
62 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo() argument
67 if (isImplicitlyDef(MRI, MO.getReg())) in RegSeqInfo()
82 MachineRegisterInfo *MRI; member in __anonc979ecad0111::R600VectorRegMerger
186 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass); in RebuildVector()
213 for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), in RebuildVector()
214 E = MRI->use_end(); It != E; ++It) { in RebuildVector()
261 for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), in areAllUsesSwizzeable()
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| D | AMDGPUIndirectAddressing.cpp | 37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const;
60 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction() local
106 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); in runOnMachineFunction()
121 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); in runOnMachineFunction()
188 unsigned PhiDstReg = MRI.createVirtualRegister(PhiDstClass); in runOnMachineFunction()
197 MachineInstr *DefInst = MRI.getVRegDef(Reg); in runOnMachineFunction()
246 unsigned IndirectReg = MRI.createVirtualRegister(SuperIndirectRegClass); in runOnMachineFunction()
257 if (regHasExplicitDef(MRI, Reg)) { in runOnMachineFunction()
294 if (!regHasExplicitDef(MRI, Reg)) { in runOnMachineFunction()
320 bool AMDGPUIndirectAddressingPass::regHasExplicitDef(MachineRegisterInfo &MRI, in regHasExplicitDef() argument
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 94 MachineRegisterInfo *MRI; member in __anon8c8bd9350111::PeepholeOptimizer
158 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
181 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
193 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
264 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
269 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
279 MRI->clearKillFlags(DstReg); in INITIALIZE_PASS_DEPENDENCY()
280 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
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| D | RegAllocBase.cpp | 57 MRI = &vrm.getRegInfo(); in init()
61 MRI->freezeReservedRegs(vrm.getMachineFunction()); in init()
70 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in seedLiveRegs()
72 if (MRI->reg_nodbg_empty(Reg)) in seedLiveRegs()
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
101 << MRI->getRegClass(VirtReg->reg)->getName() in allocatePhysRegs()
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg); in allocatePhysRegs()
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
133 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { in allocatePhysRegs()
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| D | VirtRegMap.cpp | 53 MRI = &mf.getRegInfo(); in runOnMachineFunction()
81 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
90 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
118 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
123 << MRI->getRegClass(Reg)->getName() << "\n"; in print()
127 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { in print()
131 << "] " << MRI->getRegClass(Reg)->getName() << "\n"; in print()
158 MachineRegisterInfo *MRI; member in __anon965f13410111::VirtRegRewriter
206 MRI = &MF->getRegInfo(); in runOnMachineFunction()
230 MRI->clearVirtRegs(); in runOnMachineFunction()
[all …]
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| D | OptimizePHIs.cpp | 31 MachineRegisterInfo *MRI; member in __anond96ccba50111::OptimizePHIs
64 MRI = &Fn.getRegInfo(); in runOnMachineFunction()
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
109 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); in IsSingleValuePHICycle()
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg), in IsDeadPHICycle()
143 E = MRI->use_end(); I != E; ++I) { in IsDeadPHICycle()
168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
171 MRI->replaceRegWith(OldReg, SingleValReg); in OptimizeBB()
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| D | MachineSink.cpp | 48 MachineRegisterInfo *MRI; // Machine register information member in __anon0062864a0111::MachineSinking
132 !MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
145 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
165 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
185 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
199 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
227 MRI = &MF.getRegInfo(); in runOnMachineFunction()
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| D | MachineCSE.cpp | 45 MachineRegisterInfo *MRI; member in __anon5ee06c100111::MachineCSE
124 if (!MRI->hasOneNonDBGUse(Reg)) in INITIALIZE_PASS_DEPENDENCY()
128 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY()
136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) in INITIALIZE_PASS_DEPENDENCY()
141 MRI->clearKillFlags(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
209 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent())) in hasLivePhysRegDefUses()
261 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i])) in PhysRegDefsReach()
352 for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg), in isProfitableToCSE()
353 E = MRI->use_nodbg_end(); I != E; ++I) { in isProfitableToCSE()
357 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg), in isProfitableToCSE()
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| D | DeadMachineInstructionElim.cpp | 33 const MachineRegisterInfo *MRI; member in __anonb39192cc0111::DeadMachineInstructionElim
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) in isDead()
75 if (!MRI->use_nodbg_empty(Reg)) in isDead()
88 MRI = &MF.getRegInfo(); in runOnMachineFunction()
100 LivePhysRegs = MRI->getReservedRegs(); in runOnMachineFunction()
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), in runOnMachineFunction()
132 E = MRI->use_end(); I!=E; I=nextI) { in runOnMachineFunction()
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| D | RegisterPressure.cpp | 50 const MachineRegisterInfo *MRI) { in increase() argument
52 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in increase()
66 const MachineRegisterInfo *MRI) { in decrease() argument
68 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in decrease()
119 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]); in increaseRegPressure()
136 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]); in decreaseRegPressure()
216 MRI = &MF->getRegInfo(); in init()
238 LiveRegs.VirtRegs.setUniverse(MRI->getNumVirtRegs()); in init()
241 UntiedDefs.setUniverse(MRI->getNumVirtRegs()); in init()
331 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in initLiveThru()
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| D | LiveRangeEdit.cpp | 34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom()
89 if (MRI.isConstantPhysReg(MO.getReg(), *OrigMI->getParent()->getParent())) in allUsesAvailableAt()
164 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg), in foldAsLoad()
165 E = MRI.reg_nodbg_end(); I != E; ++I) { in foldAsLoad()
254 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg)) in eliminateDeadDef()
257 for (MCRegUnitIterator Units(Reg, MRI.getTargetRegisterInfo()); in eliminateDeadDef()
274 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) || in eliminateDeadDef()
319 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
382 ConEQ.Distribute(&Dups[0], MRI); in eliminateDeadDefs()
397 if (MRI.recomputeRegClass(LI.reg, MF.getTarget())) in calculateRegClassAndHint()
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| D | MachineSSAUpdater.cpp | 41 MRI = &MF.getRegInfo(); in MachineSSAUpdater()
57 VRC = MRI->getRegClass(VR); in Initialize()
115 MachineRegisterInfo *MRI, in InsertNewDef() argument
117 unsigned NewVR = MRI->createVirtualRegister(RC); in InsertNewDef()
151 VRC, MRI, TII); in GetValueInMiddleOfBlock()
187 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
234 MRI->replaceRegWith(OldReg, NewReg); in ReplaceRegWith()
298 Updater->VRC, Updater->MRI, in GetUndefVal()
309 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
332 return InstrIsPHI(Updater->MRI->getVRegDef(Val)); in ValueIsPHI()
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| D | MachineLICM.cpp | 68 MachineRegisterInfo *MRI; member in __anon84e169da0111::MachineLICM
328 MRI = &MF.getRegInfo(); in runOnMachineFunction()
331 PreRegAlloc = MRI->isSSA(); in runOnMachineFunction()
772 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) { in isOperandKill() argument
773 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg()); in isOperandKill()
782 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in getRegisterClassIDAndCost()
827 bool isKill = isOperandKill(MO, MRI); in InitRegPressure()
856 else if (!isNew && isOperandKill(MO, MRI)) { in UpdateRegPressure()
938 if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent())) in IsLoopInvariantInst()
955 assert(MRI->getVRegDef(Reg) && in IsLoopInvariantInst()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 63 MachineRegisterInfo *MRI; member
146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
164 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
230 for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg), in eraseInstrWithNoUses()
231 EE = MRI->use_end(); in eraseInstrWithNoUses()
263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
283 MRI->getRegClass(MI->getOperand(1).getReg()); in optimizeSDPattern()
284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
315 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
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| D | MLxExpansionPass.cpp | 52 MachineRegisterInfo *MRI; member
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
119 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
123 MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg); in getDefReg()
130 !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
132 UseMI = &*MRI->use_nodbg_begin(Reg); in getDefReg()
148 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
159 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 147 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI) in verifyLeafProcRegUse() argument
151 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
155 if (MRI->isPhysRegUsed(reg)) in verifyLeafProcRegUse()
164 MachineRegisterInfo &MRI = MF.getRegInfo(); in isLeafProc() local
168 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed in isLeafProc()
169 || MRI.isPhysRegUsed(SP::O6) // %SP is used in isLeafProc()
175 MachineRegisterInfo &MRI = MF.getRegInfo(); in remapRegsForLeafProc() local
179 if (!MRI.isPhysRegUsed(reg)) in remapRegsForLeafProc()
182 assert(!MRI.isPhysRegUsed(mapped_reg)); in remapRegsForLeafProc()
185 MRI.replaceRegWith(reg, mapped_reg); in remapRegsForLeafProc()
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 48 const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(Triple); in LLVMCreateDisasmCPU() local
49 if (!MRI) in LLVMCreateDisasmCPU()
53 const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, Triple); in LLVMCreateDisasmCPU()
70 MCContext *Ctx = new MCContext(MAI, MRI, 0); in LLVMCreateDisasmCPU()
93 *MAI, *MII, *MRI, *STI); in LLVMCreateDisasmCPU()
99 TheTarget, MAI, MRI, in LLVMCreateDisasmCPU()
224 const MCRegisterInfo *MRI = DC->getRegisterInfo(); in LLVMSetDisasmOptions() local
229 AsmPrinterVariant, *MAI, *MII, *MRI, *STI); in LLVMSetDisasmOptions()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 65 MachineRegisterInfo *MRI; member
302 MRI = &MF.getRegInfo(); in runOnMachineFunction()
355 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister()
363 if (MRI->getVRegDef(IndReg) == Phi) { in findInductionRegister()
382 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
418 IVOp = MRI->getVRegDef(F->first); in findInductionRegister()
469 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount()
501 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
593 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount()
596 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount()
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | AMDGPUMCTargetDesc.cpp | 69 const MCRegisterInfo &MRI, in createAMDGPUMCInstPrinter() argument
71 return new AMDGPUInstPrinter(MAI, MII, MRI); in createAMDGPUMCInstPrinter()
75 const MCRegisterInfo &MRI, in createAMDGPUMCCodeEmitter() argument
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); in createAMDGPUMCCodeEmitter()
81 return createR600MCCodeEmitter(MCII, MRI, STI); in createAMDGPUMCCodeEmitter()
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| D | R600MCCodeEmitter.cpp | 37 const MCRegisterInfo &MRI; member in __anon094eb6db0111::R600MCCodeEmitter
44 : MCII(mcii), MRI(mri), STI(sti) { } in R600MCCodeEmitter()
85 const MCRegisterInfo &MRI, in createR600MCCodeEmitter() argument
87 return new R600MCCodeEmitter(MCII, MRI, STI); in createR600MCCodeEmitter()
163 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT; in getHWRegChan()
167 return MRI.getEncodingValue(RegNo) & HW_REG_MASK; in getHWReg()
175 return MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
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