| /external/llvm/lib/Target/R600/ |
| D | AMDGPUIndirectAddressing.cpp | 303 MachineInstrBuilder Mov = TII->buildIndirectRead(BB, I, in runOnMachineFunction() local
310 Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill); in runOnMachineFunction()
311 Mov.addReg(LiveAddressRegisterMap[Address], RegState::Implicit); in runOnMachineFunction()
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| D | R600InstrInfo.cpp | 1052 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectWrite() local
1056 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1); in buildIndirectWrite()
1057 return Mov; in buildIndirectWrite()
1069 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectRead() local
1074 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1); in buildIndirectRead()
1076 return Mov; in buildIndirectRead()
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| D | SIISelLowering.cpp | 642 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand); in foldImm() local
645 if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode())) in foldImm()
648 const SDValue &Op = Mov->getOperand(0); in foldImm()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 668 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1, $c2, $c3;\n\t",
675 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1, $c2, $c3;\n\t",
682 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1, $c2, $c3;\n\t",
689 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1, $c2, $c3;\n\t",
696 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
703 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
710 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
717 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
724 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
731 !strconcat("//Mov $dst, $src1, $src2, $c0, $c1;\n\t",
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| /external/valgrind/main/VEX/priv/ |
| D | host_arm_defs.c | 1144 i->ARMin.Mov.dst = dst; in ARMInstr_Mov()
1145 i->ARMin.Mov.src = src; in ARMInstr_Mov()
1568 ppHRegARM(i->ARMin.Mov.dst); in ppARMInstr()
1570 ppARMRI84(i->ARMin.Mov.src); in ppARMInstr()
2013 addHRegUse(u, HRmWrite, i->ARMin.Mov.dst); in getRegUsage_ARMInstr()
2014 addRegUsage_ARMRI84(u, i->ARMin.Mov.src); in getRegUsage_ARMInstr()
2310 i->ARMin.Mov.dst = lookupHRegRemap(m, i->ARMin.Mov.dst); in mapRegs_ARMInstr()
2311 mapRegs_ARMRI84(m, i->ARMin.Mov.src); in mapRegs_ARMInstr()
2491 if (i->ARMin.Mov.src->tag == ARMri84_R) { in isMove_ARMInstr()
2492 *src = i->ARMin.Mov.src->ARMri84.R.reg; in isMove_ARMInstr()
[all …]
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| D | host_arm_defs.h | 656 } Mov; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 710 MachineInstrBuilder Mov; in copyPhysReg() local
728 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) in copyPhysReg()
732 Mov.addReg(Src); in copyPhysReg()
733 Mov = AddDefaultPred(Mov); in copyPhysReg()
736 Mov = AddDefaultCC(Mov); in copyPhysReg()
739 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
741 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
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| D | ARMScheduleA9.td | 2134 // A9WriteLfp1-8Mov adds a cycle of latency and FP resource for
2136 def A9WriteLfp#NumAddr#Mov : WriteSequence<
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