| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
78 NewOpcode = Hexagon::JMP_f; in InvertAndChangeJumpTarget()
82 NewOpcode = Hexagon::JMP_t; in InvertAndChangeJumpTarget()
86 NewOpcode = Hexagon::JMP_fnew_t; in InvertAndChangeJumpTarget()
90 NewOpcode = Hexagon::JMP_tnew_t; in InvertAndChangeJumpTarget()
97 MI->setDesc(QII->get(NewOpcode)); in InvertAndChangeJumpTarget()
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| D | HexagonVLIWPacketizer.cpp | 438 int NewOpcode; in PromoteToDotNew() local
440 NewOpcode = QII->GetDotNewPredOp(MI, MBPI); in PromoteToDotNew()
442 NewOpcode = QII->GetDotNewOp(MI); in PromoteToDotNew()
443 MI->setDesc(QII->get(NewOpcode)); in PromoteToDotNew()
450 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); in DemoteToDotOld() local
451 MI->setDesc(QII->get(NewOpcode)); in DemoteToDotOld()
771 int NewOpcode = QII->GetDotNewOp(MI); in CanPromoteToDotNew() local
772 const MCInstrDesc &desc = QII->get(NewOpcode); in CanPromoteToDotNew()
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| D | HexagonInstrInfo.cpp | 1581 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in GetDotNewPredOp() local
1582 if (NewOpcode >= 0) // Valid predicate new instruction in GetDotNewPredOp()
1583 return NewOpcode; in GetDotNewPredOp()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 219 int NewOpcode; in eliminateFrameIndex() local
221 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in eliminateFrameIndex()
222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in eliminateFrameIndex()
226 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in eliminateFrameIndex()
227 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in eliminateFrameIndex()
232 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in eliminateFrameIndex()
233 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in eliminateFrameIndex()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 39 unsigned NewOpcode) const { in splitMove()
61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
80 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
81 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
503 unsigned NewOpcode; in convertToThreeAddress() local
505 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
507 NewOpcode = SystemZ::RISBLG32; in convertToThreeAddress()
511 NewOpcode = 0; in convertToThreeAddress()
[all …]
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| D | SystemZFrameLowering.cpp | 436 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
440 if (!NewOpcode) { in emitEpilogue()
445 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
446 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
449 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
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| D | SystemZInstrInfo.h | 109 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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| /external/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 224 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
226 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
228 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
229 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
232 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
234 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
465 int NewOpcode, DebugLoc DL) { in insertInstrEnd() argument
467 ->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
474 int NewOpcode, DebugLoc DL) { in insertInstrBefore() argument
476 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
[all …]
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| D | SIISelLowering.cpp | 1041 unsigned NewOpcode = N->getMachineOpcode(); in AdjustRegClass() local
1046 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64; in AdjustRegClass()
1049 if (NewOpcode == N->getMachineOpcode()) { in AdjustRegClass()
1050 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; in AdjustRegClass()
1055 if (NewOpcode == N->getMachineOpcode()) { in AdjustRegClass()
1056 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; in AdjustRegClass()
1068 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops); in AdjustRegClass()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 214 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); in EncodeInstruction() local
215 if (NewOpcode != -1) { in EncodeInstruction()
216 Opcode = NewOpcode; in EncodeInstruction()
217 TmpInst.setOpcode (NewOpcode); in EncodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 260 unsigned NewOpcode = 0; in SimplifyMOVSX() local
267 NewOpcode = X86::CBW; in SimplifyMOVSX()
271 NewOpcode = X86::CWDE; in SimplifyMOVSX()
275 NewOpcode = X86::CDQE; in SimplifyMOVSX()
279 if (NewOpcode != 0) { in SimplifyMOVSX()
281 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
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| D | X86InstrInfo.cpp | 3366 unsigned NewOpcode = 0; in optimizeCompareInstr() local
3389 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
3390 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
3391 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
3392 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
3393 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
3394 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
3395 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
3396 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
3397 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 1201 std::string NewOpcode; in ParseInstruction() local
1204 NewOpcode = Name; in ParseInstruction()
1205 NewOpcode += '+'; in ParseInstruction()
1206 Name = NewOpcode; in ParseInstruction()
1210 NewOpcode = Name; in ParseInstruction()
1211 NewOpcode += '-'; in ParseInstruction()
1212 Name = NewOpcode; in ParseInstruction()
1218 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1226 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 672 unsigned NewOpcode = in EmitInstruction() local
676 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) in EmitInstruction()
686 unsigned NewOpcode = in EmitInstruction() local
692 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) in EmitInstruction()
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| D | PPCRegisterInfo.cpp | 671 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
672 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3487 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3491 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
3499 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3503 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
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