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Searched refs:OpNode (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h78 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
80 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
82 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
85 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td169 multiclass I3<string OpcStr, SDNode OpNode> {
172 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
176 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
179 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
183 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
193 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
197 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
201 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
DNVPTXVector.td241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
245 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
252 [(set regclass1:$dst, (OpNode regclass1:$a, regclass2:$b))],
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
259 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
266 def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
268 def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
[all …]
DNVPTXISelDAGToDAG.cpp2334 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRsi_imp() argument
2348 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr, in SelectADDRsi() argument
2350 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRsi()
2354 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr, in SelectADDRsi64() argument
2356 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRsi64()
2361 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) { in SelectADDRri_imp() argument
2390 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr, in SelectADDRri() argument
2392 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32); in SelectADDRri()
2396 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr, in SelectADDRri64() argument
2398 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64); in SelectADDRri64()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
264 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
268 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
274 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
278 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
284 list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
288 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
298 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
304 list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td93 SDPatternOperator OpNode= null_frag> :
96 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
101 SDPatternOperator OpNode = null_frag> {
102 def _D32 : ADDS_FT<opstr, AFGR64RegsOpnd, Itin, IsComm, OpNode>,
104 def _D64 : ADDS_FT<opstr, FGR64RegsOpnd, Itin, IsComm, OpNode>,
111 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
113 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
117 SDPatternOperator OpNode= null_frag> {
118 def _D32 : ABSS_FT<opstr, AFGR64RegsOpnd, AFGR64RegsOpnd, Itin, OpNode>,
120 def _D64 : ABSS_FT<opstr, FGR64RegsOpnd, FGR64RegsOpnd, Itin, OpNode>,
[all …]
DMipsInstrInfo.td383 SDPatternOperator OpNode = null_frag>:
386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
395 SDPatternOperator OpNode = null_frag> :
398 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
423 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
427 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
430 SDPatternOperator OpNode = null_frag>:
433 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
452 class Load<string opstr, SDPatternOperator OpNode, DAGOperand RO,
456 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
[all …]
DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMips16InstrInfo.td1233 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1234 Mips16Pat<(OpNode CPU16Regs:$r),
1240 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1241 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1253 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1254 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1263 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1264 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1271 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1272 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrFMA.td120 SDPatternOperator OpNode = null_frag> {
127 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
134 (OpVT (OpNode RC:$src2, RC:$src1,
159 SDNode OpNode, RegisterClass RC, ValueType OpVT,
170 x86memop, RC, OpVT, mem_frag, OpNode>,
177 SDNode OpNode> {
178 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", IntF32, OpNode,
180 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", IntF64, OpNode,
201 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
209 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, MemOp4;
[all …]
DX86InstrAVX512.td545 RegisterClass KRC, SDPatternOperator OpNode> {
549 [(set KRC:$dst, (OpNode KRC:$src))]>;
553 SDPatternOperator OpNode> {
554 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
572 RegisterClass KRC, SDPatternOperator OpNode> {
577 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
581 SDPatternOperator OpNode> {
582 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
613 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
615 def : Pat<(OpNode VK8:$src1, VK8:$src2),
[all …]
DX86InstrFPStack.td130 multiclass FPBinary_rr<SDNode OpNode> {
134 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
136 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
138 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
143 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
148 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
152 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
156 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
160 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
164 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
[all …]
DX86InstrCMovSetCC.td82 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
86 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
90 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
DX86InstrSSE.td159 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
168 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
175 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
213 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
220 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
464 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
470 [(set VR128:$dst, (vt (OpNode VR128:$src1,
482 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
485 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2327 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2330 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2333 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2336 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2373 ValueType TyD, ValueType TyQ, SDNode OpNode>
2376 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2391 ValueType TyQ, ValueType TyD, SDNode OpNode>
2394 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2420 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2424 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrFormats.td144 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
148 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
151 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
DSparcInstrInfo.td190 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
194 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
198 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td203 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
206 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
209 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
220 SDNode OpNode> {
223 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
226 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
229 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
232 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
241 SDNode OpNode> {
244 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td20 multiclass ALU32_rr_ri<string OpcStr, SDNode OpNode> {
23 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
27 [(set (i32 IntRegs:$dst), (OpNode s10Imm:$b,
33 multiclass CMP64_rr<string OpcStr, PatFrag OpNode> {
37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
40 multiclass CMP32_rr_ri_s10<string OpcStr, string CextOp, PatFrag OpNode> {
46 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
53 (OpNode (i32 IntRegs:$b), s10ExtPred:$c))]>;
57 multiclass CMP32_rr_ri_u9<string OpcStr, string CextOp, PatFrag OpNode> {
63 (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>;
[all …]
DHexagonInstrInfoV5.td174 multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
178 (OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
182 multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
186 (OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
DHexagonInstrInfoV4.td1924 InstHexagon MI, SDNode OpNode> {
1926 def : Pat < (stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
1931 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2011 SDNodeXForm xformFunc, InstHexagon MI, SDNode OpNode> {
2015 def : Pat<(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
2022 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend),
2065 PatLeaf extPred, InstHexagon MI, SDNode OpNode> {
2068 def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)),
2074 def : Pat <(stOp (OpNode (ldOp (add IntRegs:$base, extPred:$offset)),
3121 multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {
[all …]
DHexagonISelLowering.cpp942 SDNode* OpNode = Op.getNode(); in LowerSELECT_CC() local
943 EVT SVT = OpNode->getValueType(0); in LowerSELECT_CC()
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp2836 TreePatternNode *OpNode = InVal->clone(); in ParseInstructions() local
2839 OpNode->clearPredicateFns(); in ParseInstructions()
2842 if (Record *Xform = OpNode->getTransformFn()) { in ParseInstructions()
2843 OpNode->setTransformFn(0); in ParseInstructions()
2845 Children.push_back(OpNode); in ParseInstructions()
2846 OpNode = new TreePatternNode(Xform, Children, OpNode->getNumTypes()); in ParseInstructions()
2849 ResultNodeOperands.push_back(OpNode); in ParseInstructions()
3257 TreePatternNode *OpNode = DstPattern->getChild(ii); in ParsePatterns() local
3258 if (Record *Xform = OpNode->getTransformFn()) { in ParsePatterns()
3259 OpNode->setTransformFn(0); in ParsePatterns()
[all …]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIISelLowering.cpp299 SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64, in Loweri1ContextSwitch() local
305 return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode); in Loweri1ContextSwitch()
/external/mesa3d/src/gallium/drivers/radeon/
DSIISelLowering.cpp299 SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64, in Loweri1ContextSwitch() local
305 return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode); in Loweri1ContextSwitch()

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