| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() argument
340 .addImm(Pred).addReg(PredReg).addReg(0); in MergeOps()
351 .addImm(Pred).addReg(PredReg); in MergeOps()
371 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate() argument
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
448 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR() argument
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
[all …]
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| D | Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
109 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
215 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
230 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
252 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
438 unsigned PredReg; in rewriteT2FrameIndex() local
[all …]
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| D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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| D | Thumb2RegisterInfo.cpp | 39 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
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| D | ARMBaseRegisterInfo.cpp | 390 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
401 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
744 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
752 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
756 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
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| D | Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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| D | MLxExpansionPass.cpp | 284 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
297 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
309 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.h | 366 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
387 ARMCC::CondCodes Pred, unsigned PredReg,
393 ARMCC::CondCodes Pred, unsigned PredReg,
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| D | Thumb2ITBlockPass.cpp | 169 unsigned PredReg = 0; in InsertITInstructions() local
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
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| D | Thumb2SizeReduction.cpp | 583 unsigned PredReg = 0; in ReduceSpecial() local
584 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
687 unsigned PredReg = 0; in ReduceTo2Addr() local
688 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
784 unsigned PredReg = 0; in ReduceToNarrow() local
785 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
373 unsigned PredReg; in rewriteFrameIndex() local
374 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteFrameIndex()
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| D | ARMFrameLowering.cpp | 123 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate() argument
126 Pred, PredReg, TII, MIFlags); in emitSPUpdate()
129 Pred, PredReg, TII, MIFlags); in emitSPUpdate()
1418 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1420 Pred, PredReg); in eliminateCallFramePseudoInstr()
1423 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
1426 Pred, PredReg); in eliminateCallFramePseudoInstr()
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| D | ARMBaseRegisterInfo.h | 167 unsigned PredReg = 0,
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| D | ARMExpandPseudoInsts.cpp | 615 unsigned PredReg = 0; in ExpandMOV32BitImm() local
616 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
639 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
640 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
676 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
677 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
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| D | ARMConstantIslandPass.cpp | 1350 unsigned PredReg = 0; in createNewWater() local
1351 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1796 unsigned PredReg = 0; in optimizeThumb2Branches() local
1797 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1815 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
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| D | ARMBaseInstrInfo.cpp | 1579 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1582 PredReg = 0; in getInstrPredicate()
1586 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1609 unsigned PredReg = 0; in commuteInstruction() local
1610 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1612 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstruction()
1782 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
1801 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
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| D | ARMISelDAGToDAG.cpp | 2638 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2639 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2903 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2904 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2923 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2924 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2942 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2943 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); in getLoopTripCount() local
501 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount()
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