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Searched refs:R600 (Results 1 – 25 of 103) sorted by relevance

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/external/llvm/test/CodeGen/R600/
D	load.ll	1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck --check-prefix=R600-CHECK %s 2 ; RUN: llc < %s -march=r600 -mcpu=cayman \| FileCheck --check-prefix=R600-CHECK %s 10 ; R600-CHECK: @load_i8 11 ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} 22 ; R600-CHECK: @load_i8_sext 23 ; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] 24 ; R600-CHECK: LSHL {{[* ]}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] 25 ; R600-CHECK: 24 26 ; R600-CHECK: ASHR {{[ ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] 27 ; R600-CHECK: 24 [all …]
D	build_vector.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @build_vector2 5 ; R600-CHECK: MOV 6 ; R600-CHECK: MOV 7 ; R600-CHECK-NOT: MOV 18 ; R600-CHECK: @build_vector4 19 ; R600-CHECK: MOV 20 ; R600-CHECK: MOV 21 ; R600-CHECK: MOV 22 ; R600-CHECK: MOV [all …]`
D	128bit-kernel-args.ll	1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @v4i32_kernel_arg 5 ; R600-CHECK-DAG: MOV {{[* ]}}T[[GPR:[0-9]]].X, KC0[3].Y 6 ; R600-CHECK-DAG: MOV {{[ ]}}T[[GPR]].Y, KC0[3].Z 7 ; R600-CHECK-DAG: MOV {{[ ]}}T[[GPR]].Z, KC0[3].W 8 ; R600-CHECK-DAG: MOV {{[ ]}}T[[GPR]].W, KC0[4].X 17 ; R600-CHECK: @v4f32_kernel_arg 18 ; R600-CHECK-DAG: MOV {{[ ]}}T[[GPR:[0-9]]].X, KC0[3].Y 19 ; R600-CHECK-DAG: MOV {{[ ]}}T[[GPR]].Y, KC0[3].Z 20 ; R600-CHECK-DAG: MOV {{[ ]*}}T[[GPR]].Z, KC0[3].W [all …]
D	max-literals.ll	8 %0 = call float @llvm.R600.load.input(i32 4) 9 %1 = call float @llvm.R600.load.input(i32 5) 10 %2 = call float @llvm.R600.load.input(i32 6) 11 %3 = call float @llvm.R600.load.input(i32 7) 12 %4 = call float @llvm.R600.load.input(i32 8) 28 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) 37 %0 = call float @llvm.R600.load.input(i32 4) 38 %1 = call float @llvm.R600.load.input(i32 5) 39 %2 = call float @llvm.R600.load.input(i32 6) 40 %3 = call float @llvm.R600.load.input(i32 7) [all …]
D	pv-packing.ll	8 %0 = call float @llvm.R600.load.input(i32 4) 9 %1 = call float @llvm.R600.load.input(i32 5) 10 %2 = call float @llvm.R600.load.input(i32 6) 11 %3 = call float @llvm.R600.load.input(i32 8) 12 %4 = call float @llvm.R600.load.input(i32 9) 13 %5 = call float @llvm.R600.load.input(i32 10) 14 %6 = call float @llvm.R600.load.input(i32 12) 15 %7 = call float @llvm.R600.load.input(i32 13) 16 %8 = call float @llvm.R600.load.input(i32 14) 34 call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2) [all …]
D	tex-clause-antidep.ll	7 %1 = call float @llvm.R600.load.input(i32 0) 8 %2 = call float @llvm.R600.load.input(i32 1) 9 %3 = call float @llvm.R600.load.input(i32 2) 10 %4 = call float @llvm.R600.load.input(i32 3) 15 …%9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32… 16 …%10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i3… 18 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) 22 declare float @llvm.R600.load.input(i32) readnone 23 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno… 24 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
D	texture-input-merge.ll	6 %1 = call float @llvm.R600.load.input(i32 0) 7 %2 = call float @llvm.R600.load.input(i32 1) 8 %3 = call float @llvm.R600.load.input(i32 2) 9 %4 = call float @llvm.R600.load.input(i32 3) 19 …%14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 20 …%15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 21 …%16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i… 24 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) 28 declare float @llvm.R600.load.input(i32) readnone 29 declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno… [all …]
D	work-item-intrinsics.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck --check-prefix=R600-CHECK %s 4 ; R600-CHECK: @ngroups_x 5 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] 6 ; R600-CHECK: MOV * [[VAL]], KC0[0].X 18 ; R600-CHECK: @ngroups_y 19 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] 20 ; R600-CHECK: MOV * [[VAL]], KC0[0].Y 32 ; R600-CHECK: @ngroups_z 33 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] 34 ; R600-CHECK: MOV * [[VAL]], KC0[0].Z [all …]`
D	fp_to_sint.ll	1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @fp_to_sint_v2i32 5 ; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], PV\.[XYZW]}} 6 ; R600-CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} 16 ; R600-CHECK: @fp_to_sint_v4i32 17 ; R600-CHECK: FLT_TO_INT {{[* ]}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} 18 ; R600-CHECK: FLT_TO_INT {{[ ]}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} 19 ; R600-CHECK: FLT_TO_INT {{[ ]}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} 20 ; R600-CHECK: FLT_TO_INT {{[ ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
D	sint_to_fp.ll	1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @sint_to_fp_v2i32 5 ; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W 6 ; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X 16 ; R600-CHECK: @sint_to_fp_v4i32 17 ; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 18 ; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 19 ; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 20 ; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
D	uint_to_fp.ll	1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @uint_to_fp_v2i32 5 ; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W 6 ; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X 16 ; R600-CHECK: @uint_to_fp_v4i32 17 ; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 18 ; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 19 ; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 20 ; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
D	pv.ll	`8 %0 = call float @llvm.R600.load.input(i32 4) 9 %1 = call float @llvm.R600.load.input(i32 5) 10 %2 = call float @llvm.R600.load.input(i32 6) 11 %3 = call float @llvm.R600.load.input(i32 7) 12 %4 = call float @llvm.R600.load.input(i32 8) 13 %5 = call float @llvm.R600.load.input(i32 9) 14 %6 = call float @llvm.R600.load.input(i32 10) 15 %7 = call float @llvm.R600.load.input(i32 11) 16 %8 = call float @llvm.R600.load.input(i32 12) 17 %9 = call float @llvm.R600.load.input(i32 13) [all …]`
D	swizzle-export.ll	11 %0 = call float @llvm.R600.load.input(i32 4) 12 %1 = call float @llvm.R600.load.input(i32 5) 13 %2 = call float @llvm.R600.load.input(i32 6) 14 %3 = call float @llvm.R600.load.input(i32 7) 71 call void @llvm.R600.store.swizzle(<4 x float> %59, i32 60, i32 1) 76 call void @llvm.R600.store.swizzle(<4 x float> %63, i32 0, i32 2) 81 call void @llvm.R600.store.swizzle(<4 x float> %67, i32 1, i32 2) 86 call void @llvm.R600.store.swizzle(<4 x float> %71, i32 2, i32 2) 91 call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2) 100 %0 = call float @llvm.R600.load.input(i32 4) [all …]
D	rotr.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood -o - \| FileCheck --check-prefix=R600-CHECK %s 4 ; R600-CHECK: @rotr 5 ; R600-CHECK: BIT_ALIGN_INT 19 ; R600-CHECK: @rotl 20 ; R600-CHECK: SUB_INT {{\ T[0-9]+\.[XYZW]}}, literal.x 21 ; R600-CHECK-NEXT: 32 22 ; R600-CHECK: BIT_ALIGN_INT {{\ T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}`
D	load-input-fold.ll	`6 %0 = call float @llvm.R600.load.input(i32 4) 7 %1 = call float @llvm.R600.load.input(i32 5) 8 %2 = call float @llvm.R600.load.input(i32 6) 9 %3 = call float @llvm.R600.load.input(i32 7) 10 %4 = call float @llvm.R600.load.input(i32 8) 11 %5 = call float @llvm.R600.load.input(i32 9) 12 %6 = call float @llvm.R600.load.input(i32 10) 13 %7 = call float @llvm.R600.load.input(i32 11) 14 %8 = call float @llvm.R600.load.input(i32 12) 15 %9 = call float @llvm.R600.load.input(i32 13) [all …]`
D	r600-encoding.ll	`2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 \| FileCheck --check-prefix=R600-CHECK %s 4 ; The earliest R600 GPUs have a slightly different encoding than the rest of 10 ; R600-CHECK: @test 11 ; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+… 15 %0 = call float @llvm.R600.load.input(i32 0) 16 %1 = call float @llvm.R600.load.input(i32 1) 22 declare float @llvm.R600.load.input(i32) readnone`
D	bfi_int.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck --check-prefix=R600-CHECK %s 7 ; R600-CHECK: @bfi_def 8 ; R600-CHECK: BFI_INT 23 ; R600-CHECK: @bfi_sha256_ch 24 ; R600-CHECK: BFI_INT 38 ; R600-CHECK: @bfi_sha256_ma 39 ; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W 40 ; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]\|PV\.[XYZW]}}, KC0[3].X, KC0[2].W`
D	r600cfg.ll	6 %0 = call float @llvm.R600.load.input(i32 4) 7 %1 = call float @llvm.R600.load.input(i32 5) 8 %2 = call float @llvm.R600.load.input(i32 6) 9 %3 = call float @llvm.R600.load.input(i32 7) 36 call void @llvm.R600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1) 41 call void @llvm.R600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2) 46 call void @llvm.R600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4) 51 call void @llvm.R600.store.swizzle(<4 x float> %31, i32 60, i32 1) 56 call void @llvm.R600.store.swizzle(<4 x float> %35, i32 0, i32 2) 117 declare float @llvm.R600.load.input(i32) #1 [all …]
D	rv7x0_count3.ll	`6 %1 = call float @llvm.R600.load.input(i32 4) 7 %2 = call float @llvm.R600.load.input(i32 5) 8 %3 = call float @llvm.R600.load.input(i32 6) 9 %4 = call float @llvm.R600.load.input(i32 7) 33 call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2) 40 declare float @llvm.R600.load.input(i32) #1 43 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)`
D	call_fs.ll	`3 ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - \| FileCheck --check-prefix=R600-CHEC… 8 ; R600-CHECK: @call_fs 9 ; R600-CHECK: .long 257 10 ; R600-CHECK:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]`
D	zero_extend.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 4 ; R600-CHECK: @test 5 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg 6 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg`
D	fabs.ll	`1 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s --check-prefix=R600-CHECK 8 ; R600-CHECK: @fabs_free 9 ; R600-CHECK-NOT: AND 10 ; R600-CHECK: \|PV.{{[XYZW]}}\|`
D	fmad.ll	`6 %r0 = call float @llvm.R600.load.input(i32 0) 7 %r1 = call float @llvm.R600.load.input(i32 1) 8 %r2 = call float @llvm.R600.load.input(i32 2) 15 declare float @llvm.R600.load.input(i32) readnone`
D	schedule-fs-loop-nested-if.ll	`6 %0 = call float @llvm.R600.interp.input(i32 0, i32 0) 7 %1 = call float @llvm.R600.interp.input(i32 1, i32 0) 8 %2 = call float @llvm.R600.interp.input(i32 2, i32 0) 9 %3 = call float @llvm.R600.interp.input(i32 3, i32 0) 55 call void @llvm.R600.store.swizzle(<4 x float> %34, i32 0, i32 0) 77 declare float @llvm.R600.interp.input(i32, i32) #0 81 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)`
/external/llvm/lib/Target/R600/InstPrinter/
D	LLVMBuild.txt	`1 ;===- ./lib/Target/R600/InstPrinter/LLVMBuild.txt ------------ Conf ---===; 21 parent = R600 23 add_to_library_groups = R600`

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