| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 120 const MipsRegisterInfo &RegInfo = in expandLoadCCond() local
123 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
127 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
140 const MipsRegisterInfo &RegInfo = in expandStoreCCond() local
143 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
149 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
163 const MipsRegisterInfo &RegInfo = in expandLoadACC() local
166 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
171 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
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| D | Mips16ISelDAGToDAG.cpp | 72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
79 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
81 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| D | MipsISelLowering.cpp | 919 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinary() local
946 unsigned StoreVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
947 unsigned AndRes = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
948 unsigned Success = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1007 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in emitAtomicBinaryPartword() local
1018 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1019 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1020 unsigned Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1021 unsigned Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1022 unsigned NewVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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| D | MipsSEISelDAGToDAG.cpp | 115 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
126 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
127 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 52 const Thumb1RegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
86 const Thumb1RegisterInfo *RegInfo = in emitPrologue() local
96 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
97 unsigned BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
185 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
198 if (RegInfo->needsStackRealignment(MF)) in emitPrologue()
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| D | ARMFrameLowering.cpp | 43 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); in hasFP() local
53 RegInfo->needsStackRealignment(MF) || in hasFP()
137 const ARMBaseRegisterInfo *RegInfo = in emitPrologue() local
149 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
293 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) { in emitPrologue()
327 if (RegInfo->hasBasePointer(MF)) { in emitPrologue()
330 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
335 RegInfo->getBaseRegister()) in emitPrologue()
354 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); in emitEpilogue() local
364 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitEpilogue()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo(); in hasFP() local
51 RegInfo->needsStackRealignment(MF) || in hasFP()
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); in emitCalleeSavedFrameMoves() local
320 int stackGrowth = -RegInfo->getSlotSize(); in emitCalleeSavedFrameMoves()
487 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); in getCompactUnwindEncoding() local
488 unsigned FramePtr = RegInfo->getFrameRegister(MF); in getCompactUnwindEncoding()
489 unsigned StackPtr = RegInfo->getStackRegister(); in getCompactUnwindEncoding()
650 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); in emitPrologue() local
664 unsigned SlotSize = RegInfo->getSlotSize(); in emitPrologue()
665 unsigned FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
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| /external/llvm/lib/CodeGen/ |
| D | MachineFunction.cpp | 58 RegInfo = new (Allocator) MachineRegisterInfo(TM); in MachineFunction()
60 RegInfo = 0; in MachineFunction()
95 if (RegInfo) { in ~MachineFunction()
96 RegInfo->~MachineRegisterInfo(); in ~MachineFunction()
97 Allocator.Deallocate(RegInfo); in ~MachineFunction()
324 if (RegInfo) { in print()
325 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA"); in print()
326 if (!RegInfo->tracksLiveness()) in print()
343 if (RegInfo && !RegInfo->livein_empty()) { in print()
346 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { in print()
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| D | MachineInstr.cpp | 132 MachineRegisterInfo *RegInfo = 0; in ChangeToRegister() local
136 RegInfo = &MF->getRegInfo(); in ChangeToRegister()
140 if (RegInfo && WasReg) in ChangeToRegister()
141 RegInfo->removeRegOperandFromUseList(this); in ChangeToRegister()
163 if (RegInfo) in ChangeToRegister()
164 RegInfo->addRegOperandToUseList(this); in ChangeToRegister()
1202 const TargetRegisterInfo &RegInfo) { in substituteRegister() argument
1205 ToReg = RegInfo.getSubReg(ToReg, SubIdx); in substituteRegister()
1210 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1217 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
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| D | PrologEpilogInserter.cpp | 208 const TargetRegisterInfo *RegInfo = F.getTarget().getRegisterInfo(); in calculateCalleeSavedRegisters() local
213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&F); in calculateCalleeSavedRegisters()
250 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters()
253 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) { in calculateCalleeSavedRegisters()
563 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
566 RegInfo->useFPForScavengingIndex(Fn) && in calculateFrameObjectOffsets()
567 !RegInfo->needsStackRealignment(Fn)); in calculateFrameObjectOffsets()
674 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.h | 28 const NVPTXRegisterInfo RegInfo; variable
32 virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
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| D | NVPTXPrologEpilogPass.cpp | 110 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); in calculateFrameObjectOffsets() local
210 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0)) in calculateFrameObjectOffsets()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 871 const TargetRegisterInfo &RegInfo);
878 const TargetRegisterInfo *RegInfo,
883 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
889 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
895 const TargetRegisterInfo *RegInfo = 0);
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| D | MachineFunction.h | 83 MachineRegisterInfo *RegInfo;
167 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
168 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
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| D | FunctionLoweringInfo.h | 56 MachineRegisterInfo *RegInfo; variable
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| D | SelectionDAGISel.h | 49 MachineRegisterInfo *RegInfo; variable
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 213 const PPCRegisterInfo *RegInfo = in determineFrameLayout() local
230 !RegInfo->hasBasePointer(MF)) { // No special alignment. in determineFrameLayout()
300 const PPCRegisterInfo *RegInfo = in replaceFPWithRealFP() local
302 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
340 const PPCRegisterInfo *RegInfo = in emitPrologue() local
384 bool HasBP = RegInfo->hasBasePointer(MF); in emitPrologue()
695 const PPCRegisterInfo *RegInfo = in emitEpilogue() local
726 bool HasBP = RegInfo->hasBasePointer(MF); in emitEpilogue()
951 const PPCRegisterInfo *RegInfo = in processFunctionBeforeCalleeSavedScan() local
956 unsigned LR = RegInfo->getRARegister(); in processFunctionBeforeCalleeSavedScan()
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| D | PPCISelLowering.cpp | 5872 MachineRegisterInfo &RegInfo = F->getRegInfo(); in EmitAtomicBinary() local
5874 RegInfo.createVirtualRegister( in EmitAtomicBinary()
5941 MachineRegisterInfo &RegInfo = F->getRegInfo(); in EmitPartwordAtomicBinary() local
5945 unsigned PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5946 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5947 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5948 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5949 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5950 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
5951 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
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| D | PPCISelDAGToDAG.cpp | 197 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { in InsertVRSaveCode()
199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { in InsertVRSaveCode()
218 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in InsertVRSaveCode()
219 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in InsertVRSaveCode()
264 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in getGlobalBaseReg()
268 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass); in getGlobalBaseReg()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 38 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {} in MipsDisassemblerBase()
42 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } in getRegInfo()
45 OwningPtr<const MCRegisterInfo> RegInfo; member in __anon7356a6fe0111::MipsDisassemblerBase
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 358 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); in processFunctionBeforeCalleeSavedScan() local
377 if (RegInfo->requiresRegisterScavenging(MF)) { in processFunctionBeforeCalleeSavedScan()
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| D | XCoreISelLowering.cpp | 754 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); in LowerFRAMEADDR() local
756 RegInfo->getFrameRegister(MF), MVT::i32); in LowerFRAMEADDR()
1076 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in LowerCCCArguments() local
1119 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments()
1120 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1172 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); in LowerCCCArguments()
1173 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 382 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in getGlobalBaseReg() local
384 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in getGlobalBaseReg()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 41 OwningPtr<const MCRegisterInfo> RegInfo; member in __anon81a03cfe0111::AArch64Disassembler
46 : MCDisassembler(STI), RegInfo(Info) { in AArch64Disassembler()
59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } in getRegInfo()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 63 RegInfo = &MF->getRegInfo(); in set()
212 return RegInfo-> in CreateReg()
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