| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
342 ISD::SELECT_CC, in LowerBR_CC()
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
508 ISD::SELECT_CC, in LowerSETCC()
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| D | SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SITargetLowering()
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SITargetLowering()
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SITargetLowering()
60 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
400 case ISD::SELECT_CC: { in PerformDAGCombine()
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| D | AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand); in InitAMDILLowering()
289 case ISD::SELECT_CC: in computeMaskedBitsForTargetNode()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
342 ISD::SELECT_CC, in LowerBR_CC()
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
508 ISD::SELECT_CC, in LowerSETCC()
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| D | SIISelLowering.cpp | 56 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SITargetLowering()
57 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SITargetLowering()
59 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SITargetLowering()
60 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
400 case ISD::SELECT_CC: { in PerformDAGCombine()
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| D | AMDILISelLowering.cpp | 170 setOperationAction(ISD::SELECT_CC, VT, Expand); in InitAMDILLowering()
289 case ISD::SELECT_CC: in computeMaskedBitsForTargetNode()
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
95 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
488 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
854 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
900 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
931 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
933 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
940 return DAG.getNode(ISD::SELECT_CC, in LowerSELECT()
1407 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
[all …]
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| D | SIISelLowering.cpp | 73 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SITargetLowering()
74 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SITargetLowering()
76 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in SITargetLowering()
90 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
348 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
557 case ISD::SELECT_CC: { in PerformDAGCombine()
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| D | AMDILISelLowering.cpp | 155 setOperationAction(ISD::SELECT_CC, VT, Expand); in InitAMDILLowering()
263 case ISD::SELECT_CC: in computeMaskedBitsForTargetNode()
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2010-04-09-NeonSelect.ll | 2 ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values.
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.td | 336 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
339 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
341 "# SELECT_CC PSEUDO!",
1172 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1175 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1178 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1180 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1182 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1184 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1186 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
[all …]
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| D | XCoreISelLowering.cpp | 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in XCoreTargetLowering()
97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in XCoreTargetLowering()
179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1299 assert((MI->getOpcode() == XCore::SELECT_CC) && in EmitInstrWithCustomInserter()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 331 SELECT_CC, enumerator
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
873 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSETCC()
896 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); in LowerSELECT_CC()
1042 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 62 SELECT_CC, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 107 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
108 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
110 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
235 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
814 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC"; in getTargetNodeName()
2242 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT_CC()
2254 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, in LowerSELECT_CC()
2260 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT_CC()
2285 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), in LowerSELECT()
[all …]
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| D | AArch64ISelLowering.h | 71 SELECT_CC, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1329 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in HexagonTargetLowering()
1330 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in HexagonTargetLowering()
1340 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in HexagonTargetLowering()
1341 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in HexagonTargetLowering()
1342 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in HexagonTargetLowering()
1352 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); in HexagonTargetLowering()
1565 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 513 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
515 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
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| D | LegalizeFloatTypes.cpp | 97 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
536 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
615 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
790 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1257 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
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| D | SelectionDAGDumper.cpp | 187 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
292 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
499 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
1443 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
2160 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in WidenVecRes_SELECT_CC()
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| D | LegalizeIntegerTypes.cpp | 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
505 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteIntRes_SELECT_CC()
795 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1099 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2476 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
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| D | LegalizeDAG.cpp | 1189 case ISD::SELECT_CC: in LegalizeOp()
1192 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
1200 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3635 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3641 case ISD::SELECT_CC: { in ExpandNode()
3654 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, in ExpandNode()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1301 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1302 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1303 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1311 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1808 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
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